| Project/Area Number |
07558036
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 試験 |
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| Research Field |
計算機科学
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| Research Institution | The University of Tokyo (1996)
Tokyo Institute of Technology (1995) |
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Principal Investigator |
NANYA Takashi The University of Tokyo, Research Center for Advanced Science and Technology, Professor, 先端科学技術研究センター, 教授 (80143684)
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| Co-Investigator(Kenkyū-buntansha) |
FUKUMA Masao NEC Corporation, Microelectronics Research Lab., Senior Manager, マイクロエレクトロニクス研究所, システムULSI研究
KAGOTANI Hiroto Okayama University, Faculty of Engineering, Assistant, 工学部, 助手 (50271060)
UENO Yoichiro Tokyo Institute of Technology, Graduate School of Information Science and Engine, 大学院・情報理工学研究科, 助手 (70262285)
YONEDA Tomohiro Tokyo Institute of Technology, Graduate School of Information Science Engineerin, 大学院・情報理工学研究科, 助教授 (30182851)
FUJIWARA Eiji Tokyo Institute of Technology, Graduate School of Information Science and Engine, 大学院・情報理工学研究科, 教授 (20211526)
山田 八郎 日本電気(株), マイクロエレクトロニクス研究所, 研究専門課長
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| Project Period (FY) |
1995 – 1996
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| Project Status |
Completed (Fiscal Year 1996)
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| Budget Amount *help |
¥8,700,000 (Direct Cost: ¥8,700,000)
Fiscal Year 1996: ¥3,000,000 (Direct Cost: ¥3,000,000)
Fiscal Year 1995: ¥5,700,000 (Direct Cost: ¥5,700,000)
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| Keywords | Asynchronous Processor / Asynchronous Circuit / Asynchronous VLSI System / ALSI System Design / Asynchronous Logic Synthesis / Asynchronous Circuit Testing |
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| Research Abstract |
A 32-bit asynchronous microprocessor, whose architecture was borrowed from the MIPS R2000 processor, has been fabricated using 3 layr metal, 0.5 micron rule CMOS standard cell technology, integrating 496,367 MOS transistors and 8.6K Byte memory macro in 12.5 mm x 12.5mm. The processor chip works correctly with its power supply voltage being varied through the range from 1.5V to 6.0V and the temperature of its package surface being heated up to about 85 degrees Celsius by hair dryer and cooled down with liquid nitrogen, and achieves 52 VAX MIPS using the Dhrystone V2.1 benchmark with a power consumption of 2W at 3.3 V for room temperature. A significant feature of the design is the introduction of a new delay model, called the Scalable-Delay-Insensitive (SDI) model, which provides with a reasonable approach to dependable and high-performance asynchronous VLSI system design. the delay-insensitivity and the high-performance that the processor has been proved to achieve demonstrate that the asynchronous event-driven approach is very promising and encouraging for high-preformance VLSI system design with future device technologies.
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