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Development of a Computing System by a Functional Memory Type Parallel Processor.

Research Project

Project/Area Number 07558039
Research Category

Grant-in-Aid for Scientific Research (A)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 計算機科学
Research InstitutionKYOTO UNIVERSITY

Principal Investigator

TAMARU Keikichi  KYOTO UNIVERSITY,Department of Electronics & Communication, Professor, 工学研究科, 教授 (10127102)

Co-Investigator(Kenkyū-buntansha) YOSHIDA Toyohiko  Mitsubishi Electric Corporation, Manager, システムLSI開発研究所, 主事
KOBAYASHI Kazutoshi  KYOTO UNIVERSITY,Department of Electronics & Communication, Kyoto University, Re, 工学研究科, 助手 (70252476)
VASILY Moshnyaga  KYOTO UNIVERSITY,Department of Electronics & Communication, Kyoto University, In, 工学研究科, 講師 (40243050)
ONODERA Hidetoshi  KYOTO UNIVERSITY,Department of Electronics & Communication, Kyoto University, As, 工学研究科, 助教授 (80160927)
Project Period (FY) 1995 – 1997
Project Status Completed (Fiscal Year 1997)
Budget Amount *help
¥9,300,000 (Direct Cost: ¥9,300,000)
Fiscal Year 1997: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 1996: ¥3,800,000 (Direct Cost: ¥3,800,000)
Fiscal Year 1995: ¥4,900,000 (Direct Cost: ¥4,900,000)
KeywordsFunctional Memory / CAM / Vector Quantization / Parallel Processing / VLSI / Low Bit-rate / Image Compression / 超並列処理 / 光通信
Research Abstract

(a)Development of a Functional Memory for Addition
We develop a functional memory specialized for addtion. Its memory cell consists of a DRAM,which area is about 10 times smaller than that of an SRAM.A PE consists of two words and a bit-scrial ALU.We have designed and fabricated LSIs to evaluate is functionality and performance.
(b)Low Bit-rate Image Compression Using a Functional Memory
Here, we develop a functional memory specialized for vector quantization. It is called "FMPP-VQ", which stands for Functional Memory Type Parallel Processor for Vector Quantization. We have designed and fabricated two LSIs. One is an LSI for evaluation which consists of four PEs. The other has 64 PEs. It can be applied for low bit-rate image compression. We have developed an algorithm to send a QCIF (176*144) video sequence at 10 frames per second via a 29.2kbps line.

Report

(4 results)
  • 1997 Annual Research Report   Final Research Report Summary
  • 1996 Annual Research Report
  • 1995 Annual Research Report
  • Research Products

    (24 results)

All Other

All Publications (24 results)

  • [Publications] K.Kobayashi: "A memory-based parallel processor for vector quantization" 22nd European Solid-State Circuit Conference. 184-187 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Kobayashi: "A memory-based paralled processor for vector quantization : FMPP-VQ" IEICE Trans.on Electron. E80-C. 970-975 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] V.Moshnyaga: "実時間動き補償向け省メモリ型アレーアーキテクチャ" 電子情報通信学会論文誌. J81-D1. 77-84 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Tamaru: "An LSI for Low Bit-Rate Image Compression Using Vector Quantization" IEICE Trans.on Electron. E81-C(発表予定). (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Tamaru: "Real Time Low Bit-Rate Video Coding Algorithm Using Multi-Stage Hierarchical Vector Quantization(発表予定)" IEEE International Conference on Acoustics,Speech,and Signal Processing. (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Tamaru: "A bit-parallel block-parallel functional memory type parallel processor LSI for fast addition and Multiplication" Symposium on VLSI circuits. 61-62 (1995)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Kobayashi: "A memory-based parallel processor for vector quantization : FMPP-VQ" IEICE Trans.on Electron, Vol.E80-C. 970-975 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Tamaru: "A Low Bit-rate Image Compression Algorithm Using a Functional Memory-Type Parallel Processor for Vector Quantization" 10th Karuizawa Workshop. 291-296 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Kobayashi: "Design of a Functional Memory Type Parallel Processor for Vector Quantization." DA Synposium. 13-18 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] V.Moshnyga: "A Memory-Efficient Array Architecture for Realtime Motion Estimation." IEICE Trans.on Information and Systems. Vol.J81-D1. 77-84 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Kobayashi: "A memory-based parallel processor for vector quantization : FMPP-VQ" IEICE Trans.on Electron. E80-C. 970-975 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] V.Moshnyaga: "実時間動き補償向け省メモリ型アレーアーキテクチャ" 電子情報通信学会論文誌. J81-D1. 77-84 (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] K.Tamaru: "An LSI for Low Bit-Rate Image Compression Using Vector Quantization" IEICE Trans.on Electron. E81-C(発表予定). (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] K.Tamaru: "Real Time Low Bit-Rate Video Coding Algorithm Using Multi-Stage Hierarchical Vector Quantization" IEEE International Conference on Acoustics,Speech,and Signal Processing. (発表予定). (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] K.Tamaru: "A Global Routing Algorithm for Analog Circuits Using a Resistor Array Model" Proc.of the 1996 IEEE International Symp.on Circuits and Systems. 4. 667-670 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] K.Tamaru: "Estimation of Short-Circuit Power Dissipation and Its Influence on Propagation Delay for Static CMOS Gates" Proc.of the 1996 IEEE International Symp.on Circuits and Systems. 4. 751-754 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 小林和淑: "ベクトル量子化用機能メモリ型並列プロセッサFMPP-VQの設計" 第9回回路とシステム軽井沢ワークショップ論文集. 1. 353-358 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] V.Moshnyaga: "A Placement Driven Methodology for High-Level Syn-thesis of Sub-Micron ASIC's" Proc.of the 1996 IEEE International Symp.on Circuits and Systems. 4. 572-575 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] H.Onodera: "Timing and Power Optimization by Gate Sizing Considering False Path" Proc.of the 6th Great Lakes Symp.on VLSI. 1. 154-159 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 小野寺秀俊: "高精度アナログ素子を用いない電流モード循環型A/D変換回路" 情報処理学会DAシンポジウム'96論文集. 96. 31-34 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] K. Tamaru: "High Speed Merged Array Multiplication" J. of VLSI Signal Processing. 10. 41-52 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] K. Kobayashi: "A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor LSI for Fast Addition and Multiplication" 1995 Symposium on VLSI Circuits, Digest of Technical Papers. 1. 61-62 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] V. G. Moshnyaga: "A Scheduling Algorithm for Synthesis of Bus-Partitioned Architectures" Proc. of the ASP-DAC'95/CHDL'95/VLSI'95. 373-377 (1995)

    • Related Report
      1995 Annual Research Report
  • [Publications] H. Onodera: "An Iterative Gate Sizing Approach with Accurate Delay Evaluation" Proc. of ICCAD'95. 422-427 (1995)

    • Related Report
      1995 Annual Research Report

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Published: 1995-04-01   Modified: 2016-04-21  

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