| Project/Area Number |
07558156
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 試験 |
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| Research Field |
計算機科学
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| Research Institution | Kyoto Institute of Technology |
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Principal Investigator |
SHIBAYAMA Kiyoshi Kyoto Institute of Technology, Faculty of Engineering and Design, Professor, 工芸学部, 教授 (70127091)
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| Co-Investigator(Kenkyū-buntansha) |
NAKATA Toshiyuki NEC Corp., C&C Systems Laboratory, Manager, C&Cシステム研究所, 研究部長
OYANAGI Shigeru Toshiba Corp., Research and Development Center, Chief Specialist, 研究開発センター, 研究主幹
HIRATA Hiroaki Kyoto Institute of Technology, Faculty of Engineering and Design, Assistant Prof, 工芸学部, 助手 (90273549)
NIIMI Haruo Kyoto Institute of Technology, Faculty of Engineering and Design, Associate Prof, 工芸学部, 助教授 (40144331)
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| Project Period (FY) |
1995 – 1996
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| Project Status |
Completed (Fiscal Year 1996)
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| Budget Amount *help |
¥3,100,000 (Direct Cost: ¥3,100,000)
Fiscal Year 1996: ¥3,100,000 (Direct Cost: ¥3,100,000)
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| Keywords | Massively Parallel Computers / Processor Core / Processor Element / Thread Architecture / Message Driven / Processor Architecture |
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| Research Abstract |
Last fiscal year, we studied on the architectural design of our processor-core. Through this fiscal year, we have developed a massively parallel computer architecture which uses our processor-cores as key parts, while designing the processor-core for the implementation. In the development of a massively parallel computer, we verified the capability of the message-driven thread execution feature in our processor-core architecture to support dynamic load balancing schemes in massively parallel computers. By coupling the object-oriented paradigm with our hierarchical thread scheduling mechanism, we could succeed to balance the loads of processors in a massively parallel computer. We also proposed a novel interprocessor network architecture for massively parallel computers, and revealed its effectiveness through empirical evaluations.
In parallel with the development of the massively parallel computer architecture, we have refined the processor-core architecture. By simplifying and integrating carefully the functions essential to the processor-core, we could optimize the design of the processor-core. For example, we could dramatically eliminate the overhead which would arise if the processor-core would be composed as the combination of independent units implementing theis own functions.
We have designed the processor-core for the implementation using FPGA's. In the logic design phase of the processor-core, we used a hardware description language to describe the functions and behaviors of the processor-core, and verified the correctness of our design through logic simulations.
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