| Project/Area Number |
07650400
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | OSAKA PREFECTURE UNIVERSITY |
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Principal Investigator |
MURATA Kenji OSAKA PREFECTURE UNIVERSITY ENGINEERING,PHYSICS AND ELECTRONICS,PROFESSOR, 工学部, 教授 (30029079)
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| Co-Investigator(Kenkyū-buntansha) |
KAWATA Hiroaki OSAKA PREFECTURE UNIVERSITY ENGINEERING,PHYSICS AND ELECTRONICS,ASSISTANT PROFES, 工学部, 講師 (90186099)
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| Project Period (FY) |
1995 – 1996
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| Project Status |
Completed (Fiscal Year 1996)
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| Budget Amount *help |
¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 1996: ¥300,000 (Direct Cost: ¥300,000)
Fiscal Year 1995: ¥1,900,000 (Direct Cost: ¥1,900,000)
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| Keywords | FIELD EMITTER ARRAY / FIELD EMISSION / NICKL / SILICON / HOLOGRAFIC LITHOGRAPHY / LIFT OFF / 電子ビーム蒸着 / モリブデン / タングステン / 微細加工 |
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| Research Abstract |
It is important to develop a field emitter array (FEA) which works at low voltages with high current density. Both the gap between the emitter and the gate and the radius of the emitter curvature have to be made small in order to decrease the operating voltage. The emitter density has to be increased in order to obtain a high current density. The following experiments are performed in order to develop such novel FEAs.
(i) Fabrication of lateral nickel FEAs.
Since fine resist patterns have to be fabricated with high resolution, we use optical projection lithography with an oil immersion lens which has a high numerical aperture of 1.25. Nickel FEAs are fabricated by either lift-off technique or nickel plating by using the fabricated resist pattern. It is found that the FEA with a 0.3mum gap fabricated by the lift-off technique works from an operating voltage of 30V.The FEA with a 0.8mum gap fabricated by the nickel plating works from a voltage of 110V.
(ii) Fabrication of high density vertical silicon emitters.
Very fine resist gratings are fabricated with holographic lithography. A dots pattern can be obtained by applying a double exposure in the holographic lithography. The second exposure is done after the sample is rotated by 90ﾟ. The pattern of dots with a 0.2mum diameter and a 0.5mum period is obtained within the area of 2mm square. The density of dots is estimated as 4*10^6mm^<-2>. When a silicon substrate with the dots resist pattern is etched by CF_4 plasmas, a silicon emitter pattern with a high aspect ratio is obtained. However, the top of the emitter is not sharp. We are planing to make sharp emitters by improving the plasma etching condition and/or applying the oxidation for sharpening.
In a further study we think it will be possible to improve the fabrication process of lateral nickel FEAs which work at lower voltages and establish the fabrication process of vertical silicon FEAs.
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