| Project/Area Number |
08247104
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| Research Category |
Grant-in-Aid for Scientific Research on Priority Areas
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| Allocation Type | Single-year Grants |
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| Research Institution | University of Tokyo |
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Principal Investigator |
SAKAKI Hiroyuki Institute of Industrial Science, University of Tokyo Professor, 生産技術研究所, 教授 (90013226)
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| Co-Investigator(Kenkyū-buntansha) |
TANIGUCHI Kenji Osaka University, Department of Electronics and Information Systems, Professor, 工学研究科, 教授 (20192180)
INOUE Masataka Osaka Institute of Technology, Electrical Engineering, Professer, 電気工学科, 教授 (20029325)
TSUBOUCHI Kazuo Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授 (30006283)
AMEMIYA Yoshihito Hokkaido University, Graduate School of Engineering, Professor, 工学研究科, 教授 (80250489)
HOU Koichiro University of Tokyo, Graduate School of Frontier Sciences, Professor, 新領域創成科学研究科, 教授 (60211538)
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| Project Period (FY) |
1996 – 1999
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| Project Status |
Completed (Fiscal Year 2000)
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| Budget Amount *help |
¥191,100,000 (Direct Cost: ¥191,100,000)
Fiscal Year 1999: ¥20,800,000 (Direct Cost: ¥20,800,000)
Fiscal Year 1998: ¥35,600,000 (Direct Cost: ¥35,600,000)
Fiscal Year 1997: ¥47,700,000 (Direct Cost: ¥47,700,000)
Fiscal Year 1996: ¥87,000,000 (Direct Cost: ¥87,000,000)
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| Keywords | Single electron transistor / Quantum dot / Single electron memory / Quantum dot detector / SOI-MOS device / Binary decision diagram / Photon assisted tunneling / SET modeling / InAs系 / シングルエレクトロン多数決論理システム / 単電子FETメモリー / 非対照ターンスケール / 単電子回路シミュレータ / 単電子素子 / 量子箱 / 帯電効果 / テラヘルツ光 / 分割ゲート構造 / 単電子トランジスタ(SET) / インジウム砒素(InAs) / トンネル現象 |
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| Research Abstract |
We investigated a variety of single-electron (SE) and quantum dot (QD) devices and their circuits and systems to explore ways to achieve better performances and unprecedented functions, as summarized below.
(l) (GaAs/AlGaAs) FETs with embedded InAs QDs were newly developed. Their memory and photodetector functions were demonstrated by trapping a single electron or hole in each dot. (2) GaSb/InAs systems were selectively oxidized by a conductive AFM tip to form a SE transistor (SET) with clearcut characteristics. (3) Novel LSI-compatible fabrication method was developed to squeeze a Si SOI-MOS channel into a quantum point contact geometry. The device exhibited clear SET characteristics even at 300K and was used to form a binary-decision current switch element. (4) Improved methods to model and simulate SE transistors and memories were developed on the basis of the master rate equation or an extended SPICE framework. Bit error rates of large scale SET systems were assessed and requirements on the normalized bit energy (Eb/kT) and residual charges were clarified. Matched filter logic circuits were proposed to avoid the inherent instability of SET systems. (5) New SET architectures, such as binary decision diagrams, majority logic, and multi-valued logic using multi-electron states, were proposed and their features clarified. (6) Moreover, the response of SE and QD systems to midinfrared (MIR) and THz waves were investigated. New MIR detectors using the photoionization of trapped electrons in QDs were successfully developed. Photon assisted tunneling processes were analysed for triple- barrier SET geometries and were shown to have responsivity ten thousand times as large as that for double barrier geometries.
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