| Project/Area Number |
08405027
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
MASU Kazuya Res. Inst. Elect. Commun., TOHOKU UNIV., Associate Professor, 電気通信研究所, 助教授 (20157192)
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| Co-Investigator(Kenkyū-buntansha) |
NAKASE Hiroyuki Res. Inst. Elect. Commun., TOHOKU UNIV., Research Associate, 電気通信研究所, 助手 (60312675)
YOKOYAMA Michio Res. Inst. Elect. Commun., TOHOKU UNIV., Research Associate, 電気通信研究所, 助手 (40261573)
TSUBOUCHI Kazuo Res. Inst. Elect. Commun., TOHOKU UNIV., Professor, 電気通信研究所, 教授 (30006283)
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| Project Period (FY) |
1996 – 1999
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| Project Status |
Completed (Fiscal Year 1999)
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| Budget Amount *help |
¥41,300,000 (Direct Cost: ¥41,300,000)
Fiscal Year 1999: ¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 1998: ¥8,300,000 (Direct Cost: ¥8,300,000)
Fiscal Year 1997: ¥8,300,000 (Direct Cost: ¥8,300,000)
Fiscal Year 1996: ¥21,000,000 (Direct Cost: ¥21,000,000)
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| Keywords | Eb / No-BER characteristics / ultra-low-power design / CMOS circuits / single electron transistor / cross talk noise / low supply voltage / CSET inverter / matched filter / 高速RFバス / NO-BER特性 / 室温動作CSET / クロストーク / CMOS / 電源電圧下限値 |
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| Research Abstract |
The purpose of this research project is to establish the basis of ultra low power design of nano-scale devices on the basis of "Eb/No-BER characteristics."
1. Silicon CMOS test chips have been fabricated and their Eb/No-BER characteristics have been evaluated for the first time. Base on the measurement results, the minimum supply voltage for miniaturized CMOS circuits is proposed. Furthermore, cross-talk noises among the wiring interconnects have been estimated.
2. "Eb/No-BER characteristics" was applied to a design of single electron transistors (SET). From simulation results, peripheral parasitic capacitance and interconnect layout have been proposed as a guiding principle of nano-scale devices based on the "Eb/No-BER characteristics".
3. Complementary SET (CSET) inverter circuits were investigated from the viewpoint of room temperature operation. From the "Eb/No-BER characteristics", it has been found that room-temperature CSET is hardly implemented under up-to-date manufacturing technology.
4. Instead of normal CSET, novel matched filter type CSET has been proposed for the first time from a concept of S/N recovery. CSET which consists of 3chip matched filter has been evaluated at room temperature. Although matched filter type CSET has been proved to be effective for S/N recovery, total power consumption is found to go up. After all, it is confirmed from the "Eb/No-BER characteristics" that SET circuits is applicable to low-temperature operation.
Furthermore, ultra high-speed high-capacity bus lines for the next generation have been proposed and investigated.
We believe that the above achievements of this research fulfill the requirements for the next generation ultra low-power high-speed ULSI circuits design.
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