| Project/Area Number |
08455156
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Hokkaido University |
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Principal Investigator |
AMEMIYA Yoshihito Hokkaido Univ., Grad.School of Eng.Prof., 大学院・工学研究科, 教授 (80250489)
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| Co-Investigator(Kenkyū-buntansha) |
WU Nanjian Hokkaido Univ., Grad.School of Eng.Res.Assoc., 大学院・工学研究科, 助手 (00250481)
AKAZAWA Masamichi Hokkaido Univ., Grad.School of Eng.Assoc.Prof., 大学院・工学研究科, 助教授 (30212400)
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| Project Period (FY) |
1996 – 1997
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| Project Status |
Completed (Fiscal Year 1997)
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| Budget Amount *help |
¥8,700,000 (Direct Cost: ¥8,700,000)
Fiscal Year 1997: ¥2,300,000 (Direct Cost: ¥2,300,000)
Fiscal Year 1996: ¥6,400,000 (Direct Cost: ¥6,400,000)
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| Keywords | Single electron / SET / logic circuit / binary decision diagram / BDD / ロジック / 二部決定グラフ |
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| Research Abstract |
We proposed a method of constructing singleelectron logic systems on the basis of the binary decision diagram. Following the guiding principle that we have proposed, we designed sample logic subsystems, an adder and a comparator, by combining singleelectron BDD devices. Matters that require attention in designing the subsystems were discussed. The operation of the designed subsystems was calculated by computer simulation. It was demonstrated that the designed subsystems successfully produce an output data flow in reponse to the input data flow through pipelined processing. The operation error caused by thermal agitation was estimated. An output interface for converting single-electron transport into binary-voltage signals was also designed.
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