| Co-Investigator(Kenkyū-buntansha) |
MIURA Katsuyoshi Osaka Univ., Faculty of Engineering, Research Associate, 工学部, 助手 (30263221)
NAKAMAE Koji Osaka Univ., Faculty of Engineering, Associate Professor, 工学部, 助教授 (40155809)
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| Budget Amount *help |
¥4,800,000 (Direct Cost: ¥4,800,000)
Fiscal Year 1997: ¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 1996: ¥3,100,000 (Direct Cost: ¥3,100,000)
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| Research Abstract |
To realize the efficient fault tracing that requires only CAD layout data, we have first analyzed the hierarchical structure of the CAD layout data with the GDS II format that is widely used in the world. The layout analysis allows us to construct a cell tree where tree component cells are classified into leaf cells, primitive cells and block cells from the bottom level to the top in the tree. Next, we have proposed the hierarchical fault-tracing algorithm that is used for high levels in the tree. The algorithm allows us to trace a fault in VLSIs with bi-directional busses independently of circuit block functions where the direction of the signal flow is judged by using waveforms acquired by an EB tester. Moreover, we have proposed the fault-tracing algorithm that is used for lower levels in the tree. The method traces a fault by utilizing a layout dictionary for primitive cells and for block cells that is generated from a CAD layout data. The layout dictionary contains not only the layouts, but also cell name, its circuit function, its bounding box, the position of the input and output terminals, and the position of contacts. Among the inputs, the control lines are specified. We are now constructing an automatic fault tracing system using the proposed fault tracing algorithms. The system hardware consists of an EB test system, an LSI test system, a server computer, and a host computer which are liked by an Ethernet-based network. The system software is now implementing by integrating the programs for the fault tracing algorithms, the optimal probing point selection for waveform measurements, matching of DUT interconnection pattern with CAD layout, waveform comparison, control of the EB tester, and control of the LSI tester. We are now applying the test system to a self-made-8-bit microprocessor LSI (VDEC 1996 prototype manufacturing) to show its validity.
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