| Project/Area Number |
08455166
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | HIROSHIMA UNIVERSITY |
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Principal Investigator |
YOKOYAMA Shin Hiroshima Univ., Res. Ctr. For Nanodevices and systems, Professor, ナノデバイス・システム研究センター, 教授 (80144880)
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| Co-Investigator(Kenkyū-buntansha) |
NAGATA Makoto Hiroshima Univ., Fac. Of Eng., Research Associate, 工学部, 助手 (40274138)
MATTAUSCH Hans Jurgen Hiroshima Univ., Res. Ctr. For Nanodevices and systems, Professor, ナノデバイス・システム研究センター, 教授 (20291487)
SHIBAHARA Kentaro Hiroshima Univ., Res. Ctr. For Nanodevices and systems, Associate Professor, ナノデバイス・システム研究センター, 助教授 (50274139)
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| Project Period (FY) |
1996 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥6,800,000 (Direct Cost: ¥6,800,000)
Fiscal Year 1998: ¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 1997: ¥4,000,000 (Direct Cost: ¥4,000,000)
Fiscal Year 1996: ¥1,500,000 (Direct Cost: ¥1,500,000)
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| Keywords | optical waveguide / epitaxial lift-off / high speed / surfactant / high pressure / mounting of LED / grating coupler / optical waveguide with no crack / 発光素子層高速剥離 / AlAs剥離層膜厚依存性 / 消泡剤 / 溶液加熱 / エピタキシャルリフトオフ(ELO) / 圧力 / 信号伝送 / サファイア基板 |
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| Research Abstract |
The size of metal wires in the Large Scale Integrated Circuits (LSIs) will become very large when very high-speed signal transfer speed is realized by using the metal interconnects. In order to overcome this problem of speed and size, the optical interconnection is thought promising. In this research we have developed a few technologies to realize the optically interconnected LSI chips, such as the mounting technologies of GaAs light emitting diode. (LED) onto Si chips.
Previously the mechanical polishing had been used for thinning the GaAs LEDs, which is less practical. In this study we have employed a new technology called "Epitaxial Lift-Off (ELO) Method" to remove the GaAs LEDs from the substrate, in which the LEDs are grown by molecular beam epitaxy with a thin AlAs release layer between the LED layer and the substrate, and the AlAs layer is selectively etched in a dilute HF solution. We have improved the method and very high speed (〜18 times higher speed) ELO method was established by adding the surfactant and antifoaming agent into the etching solution, raising the temperature and applying high pressure (5 kgf/cmィイD12ィエD1). Also the GaAs mounting technology onto the Si chips was developed and we have confirmed that the mounted GaAs LEDs are not deteriorated.
Furthermore, we have developed such as design and fabrication method for grating couplers, fabrication technologies for optical waveguides with no crack, and design and fabrication method for branched waveguides. Finally the pattern matching LSI called "optically interconnected Kohonen net" was designed and fabricated. The basic operation of the fabricated test chip was confirmed.
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