| Project/Area Number |
08455167
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | KYUSHU UNIVERSITY |
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Principal Investigator |
TANIGUCHI Kenji KYUSHU UNIVERSITY,GRADUATE SCHOOL OF ISEE,PROFESSOR, 大学院・システム情報科学研究科, 教授 (10217127)
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| Co-Investigator(Kenkyū-buntansha) |
NAKASHI Kenichi KYUSHU UNIVERSITY,DEPATMENT OF EECS,ASSOCIATE PROFESSOR, 工学部, 助教授 (50237252)
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| Project Period (FY) |
1996 – 1997
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| Project Status |
Completed (Fiscal Year 1997)
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| Budget Amount *help |
¥4,200,000 (Direct Cost: ¥4,200,000)
Fiscal Year 1997: ¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 1996: ¥2,400,000 (Direct Cost: ¥2,400,000)
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| Keywords | QUANTUM EFFECT DEVICE / HEMT / RTD / MODELING / PLL / DEVICE SIMULATION / CELL LIBRARY / 機能回路 / デバイス構造 / 回路シミュレーション |
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| Research Abstract |
IN ORDER TO ESTABLISH DESIGN METHDOLOGY OF FUNCTIONAL CIRCUITS USING QUANTUM EFFCT DEVICES SUCH AS HEMT AND RTD DEVICES,WE HAVE STUDIED QUANYUM EFFECT DEVICE MODELING FOR CIRCUIT SIMULATION BASED ON PHYSICAL STRUCTURE,AND DESIGNED HEMT CELL LIBRARY FOR TOP-DOWN LSI DESIGN.AND WE HAVE ALSO DESIGNED FUNCTIONAL CIRCUITS FOCUSED ON HIGH-SPEED PLL.THE FOLLOWING RESULTS ARE OBTAINED.
1.PHYSICAL STRUCTURE BASED DEVICE MODELING
THE DEVICE MODELING BASED ON PHYSICAL STRUCTURE PREVIOUSLY PROPOSED BY THE INVESTIGATORS ARE APPLIED TO CIRCUIT SIMULATION MODEL.THE RESULTS SHOW THAT IT IS APPLICAPABLE TO CIRCUIT SIMULATION.FOR MORE WIDE VARIETY OF DEVICE STRUCTURE,DEVICE SIMULATOR IS INTRODUCED.THE METHOD TO ESTIMATE DEVICE CHARACTERISTICS AND CIRCUIT MODEL WITH DEVICE SIMULATION IS ESTABLISHED.
2.FUNCTIONAL CIRCUITS FOR PLL
PRIMITIVE GATES USING RTD/HEMT STACK STRUCTURE ARE INVESTIGATED.RTD/HEMT GATES HAVE HIGHER SPEED AND LOWER POWER CONSUMPTION CHARACTERISTICS COMPARED WITH CONVENTIONAL DCFL GATES.AND A 3-MODE PLL WHICH HAS FAST PULL-IN CHARACTERISTICS IS DESIGNED IN 0.3UM HEMT TECHNOLOGY IS DESIGNED AND SIMULATED.IT IS CONFIRMED THAT THE DESIGNED PLL CAN OPERATE UP TO 2.2 GHZ AT 1V DC POWER SUPPLY.AIMING ACHIEVE HIGHER SPEED AND LOWER POWER BY HEMT DYNAMIC CIRCUITS,PRELIMINARY INVESTIGATION ARE CARRIED OUT BY CMOS TECHNOLOGY.
3.TOP-DOWN DESIGN USING QUANTUM EFFECT DEVICES
FOR TOP-DOWN LSI DESIGN USING HEMT DEVICE,CELL LIBRARY CORRESPONDING TO FUNCTIONAL CMOS CELL LIBRARY IS DESIGNED.THE CELL LIBRARY HAS 49 BASIC CELLS WITH 1V POWER SUPPLY VOLTAGE.USING THIS CELL LIBRARY TEST CIRCUITS ARE DESIGNED BY VERILOG-HDL AND CONFIRMED.BASIC DESIGN ENVIRONMENT COMPATIBLE WITH CONVENTIONAL CMOS TO-DOWN DESIGN IS ESTABLISHED FOR HEMT LSI.
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