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VLSI Implementation for Digital Video Transmission and Compression

Research Project

Project/Area Number 08455178
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 情報通信工学
Research InstitutionOsaka University

Principal Investigator

SHIRAKAWA Isao  Osaka University, Department of Information Systems Engineering, Professor, 工学部, 教授 (10029100)

Co-Investigator(Kenkyū-buntansha) ONOYE Takao  Osaka University, Department of Information Systems Engineering, Research Assist, 工学部, 助手 (60252590)
SHIGEHIRO Yuji  Osaka University, Education Center for Information Processing, Research Assistan, 情報処理教育センター, 助手 (40243175)
ISHIURA Nagisa  Osaka University, Department of Information Systems Engineering, Associate, Prof, 工学部, 助教授 (60193265)
Project Period (FY) 1996 – 1997
Project Status Completed (Fiscal Year 1997)
Budget Amount *help
¥7,700,000 (Direct Cost: ¥7,700,000)
Fiscal Year 1997: ¥3,000,000 (Direct Cost: ¥3,000,000)
Fiscal Year 1996: ¥4,700,000 (Direct Cost: ¥4,700,000)
Keywordsdigital signal processing / VLSI implementation / MPEG / FIR filter / ディジタル記号処理 / VLSI
Research Abstract

In this project, we developed new architectures for video compression and digital filters for video transmission. We also attempted to implement VLSIs based on the architectures.
As for video compression, we developed an architecture for HDTV level MPEG2 encoder/decoder based on dedicated hardware components. We first designed for each process of video encoding/decoding a customized hardware module and then connect them with dedicated networks and memories which are optimally configured. We succeeded in integrating the encoder/decoder facilities on two VLSI chips.
As for digital filters, we developed a novel multiplication algorithm customized for digital filters and implemented a FIR as a VLSI.The algorithm enables very fast with small amount of hardware, making use of the fact that 1) only 8 to 12 bit precision is enough for the digital filters and 2) multiplicand may be a constant coefficient as long as it is programmable. An FIR filter of 11 taps is implemented as a single chip VLSI which operates at 100MHz.
We also made investigation on high-level synthesis system which expediates the design of VLSI.We developed a system which synthesizes from a specification written in C-language an RT-level VHDL description, which can be transformed automatically into layout pattern using existing logic synthesis and layout tools.

Report

(3 results)
  • 1997 Annual Research Report   Final Research Report Summary
  • 1996 Annual Research Report
  • Research Products

    (59 results)

All Other

All Publications (59 results)

  • [Publications] T.Onoye: "VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@HL" Proc.IEEE Custom Integrated Circuits Conference. 351-354 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Onoye: "A VLSI Architecture of MPEG2 MP@HL Motion Estimator" Proc.IEEE Int′l Symposium on Circuits and Systems. 664-667 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] G.Fujita: "Single Chip MPEG2 MP@ML Motion Estimator" Proc.Int′l Technical Conference on Circuits/Systems,Computers and Communications. 286-289 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Miyanohana: "VLSI Architecture for Very Low Bitrate Video Encoder Core" Proc.Int′l Technical Conference on Circuits/Systems,Computers and Communications. 294-297 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] S.Nakamura: "High-Level Synthesis System for Behavioral Descriptions with Conditional Branches" Proc.Int′l Technical Conference on Circuits/Systems,Computers and Communications. 935-938 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Y.Shigehiro: "Automatic Layout Recycling Based on Layout Description and Linear Programming" IEEE Trans.Computer-Aided Design of Integrated Circuits and Systems. 15,8. 959-967 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Onoye: "Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@HL" IEICE Trans.Fundamentals of Electronics,Communications and Computer Sciences. E79-A,8. 1210-1216 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Onoye: "A Single Chip Motion Estimator Dedicated to MPEG2 MP@HL" Proc.European Signal Processing Conference. 1479-1482 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Y.Yoshida: "Low-Power Consumption Architecture for Embedded Processor" Proc.2nd International Conference on ASIC. 77-80 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Miyanohana: "Implementation of Very Low Bitrate Video Encoder Core" Proc.2nd International Conference on ASIC. 131-134 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] G.Fujita: "Implementation of Half-Pel Precision Motion Estimator for MPEG2 MP@HL" Proc.IEEE Region 10 International Conference on Digital Signal Processing Applications(TENCON ′96). 949-954 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Miyanohana: "VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding" Proc.IEEE Asia Pacific Conference on Circuits and Systems(APCCAS ′96). 480-483 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Okada: "A High Performance Multiplier and Its Application to an FIR Filter Dedicated to Digital Video Transmission" IEICE Trans.Fundamentals of Electronics,Communications and Computer Sciences. E79-A,12. 2106-2111 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] S.Morikawa: "A High Performance FIR Filter Dedicated to Digital Video Transmission" Proc.IEEE/ACM Asia and South Pacific Design Automation Conference(ASP-DAC ′97). 77-82 (1996)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Miyanohana: "VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication" Proc.IEEE Custom Integrated Circuits Conference. 229-232 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] G.Fujita: "A New Motion Estimation Core Dedicated to H.263 Video Coding" Proc.IEEE International Symposium on Circuits and Systems. 1161-1164 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] M.H.Miki: "Low-Power H.263 Video CoDec Dedicated to Mobile Computing" Proc.International Symposium on Low Power Electronics and Design. 80-83 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Onoye: "Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing" Proc.Asia and South Pacific Design Automation Conference. 589-594 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] M.Yamaguchi: "Architecture Evaluation Based on the Datapath Structure and Parallel Constraint" IEICE Trans.Fundamentals. E80-A,10. 1853-1860 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] M.Yamaguchi: "An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint" Proc.IEEE International Symposium on Circuits and Systems. 1584-1587 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] M.Yamaguchi: "Binding and Scheduling Algorithms for Highly Retargetable Compilation" Proc.Asia and South Pacific Design Automation Conference. 93-98 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Y.Yoshida: "An Object Code Compression Approach to Embedded Processors" Proc.International Symposium on Low Power Electronics and Design. 265-268 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] N.Ishiura: "Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning" Proc.Workshop on Synthesis and System Integration of Mixed Technologies. 105-109 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Onoye, G.Fujita, M.Takatsu, I.Shirakawa, K.Matsumura, H.Ariyoshi, and S.Tsukiyama: "VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@HL" Proc.IEEE Custom Integrated Circuits Conference. 351-354 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Onoye, G.Fujita, M.Takatsu, I.Shirakawa, K.Matsumura, H.Ariyoshi, and S.Tsukiyama: "A VLSI Architecture of MPEG2 MP@HL Motion Estimator" Proc.IEEE Int'l Symposium on Circuits and Systems. 664-667 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] G.Fujita, H.Okuhata, Y.Nakatani, T.Onoye, and I.Shirakawa: "Single Chip MPEG2 MP@ML Motion Estimator" Proc.Int'l Technical Conference on Circuits/Systems, Computers and Communications. 286-289 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Miyanohana, G.Fujita, T.Onoye, and I.Shirakawa: "VLSI Architecture for Very Low Bitrate Video Encoder Core" Proc.Int'l Technical Conference on Circuits/Systems, Computers and Communications. 294-297 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] S.Nakamura, N.Ishiura, T.Yamamoto, and I.Shirakawa: "High-Level Synthesis System for Behavioral Descriptions with Conditional Branches" Proc.Int'l Technical Conference on Circuits/Systems, Computers and Communications. 935-938 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Y.Shigehiro, T.Nagata, I.Shirakawa, I.Arungsrisangchai, and H.Takahashi: "Automatic Layout Recycling Based on Layout Description and Linear Programming" IEEE Trans.Computer-Aided Design of Integrated Circuits and Systems. Vol.15, no.8. 959-967 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Onoye, G.Fujita, M.Takatsu, I.Shirakawa, and N.Yamai: "Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@HL" IEICE Trans.Fundamentals of Electronics, Communications and Computer Sciences. vol.E79-A,no.8. 1210-1216 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Onoye, G.Fujita, M.Takatsu, I.Shirakawa, and K.Matsumura: "A Single Chip Motion Estimator Dedicated to MPEG2 MP@HL" Proc.European Signal Processing Conference. 1479-1482 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Y.Yoshida, B.Y.Song, H.Okuhata, T.Onoye, and I.Shirakawa: "Low-Power Consumption Architecture for Embedded Processor" Proc.2nd International Conference on ASIC. 77-80 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Miyanohara, G.Fujita, T.Onoye, and I.Shirakawa: "Implementation of Very Low Bitrate Video Encoder Core" Proc.2nd International Conference on ASIC. 131-134 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] G.Fujita, T.Onoye, I.Shirakawa, S.Tsukiyama, and K.Matsumura: "Implementation of Half-Pel Precision Motion Estimator for MPEG2 MP@HL" Proc.IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96). 949-954 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Miyanohana, G.Fujita, T.Onoye, and I.Shirakawa: "VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding" Proc.IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96). 480-483 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Okada, S.Morikawa, S.Takeuchi, and I.Shirakawa: "A High Performance Multiplier and Its Application to an FIR Filter Dedicated to Digital Video Transmission" IEICE Trans.Fundamentals of Electronics, Communications and Computer Sciences. vol.E79-A,no.12. 2106-2111 (1996)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] S.Morikawa, K.Okada, S.Takeuchi, I.Shirakawa: "A High Performance FIR Filter Dedicated to Digital Video Transmission" Proc.IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97). 77-82 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Miyanohana, G.Fujita, K.Yanagida, T.Onoye, and I.Shirakawa: "VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication" Proc.IEEE Custom Integrated Circuits Conference. 229-232 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] G.Fujita, T.Onoye, and I.Shirakawa: "A New Motion Estimation Core Dedicated to H.263 VideoCoding" Proc.IEEE International Symposium on Circuits and Systems. 1161-1164 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] M.Yamaguchi, T.Nakaoka, A.Yamada, and T.Kambe: "An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint" Proc.IEEE International Symposium on Circuits and Systems. 1584-1587 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] M.H.Miki, G.Fujita, T.Onoye, and I.Shirakawa: "Low-Power H.263 Video CoDec Dedicated to Mobile Computing" Proc.International Symposium on Low Power Electronics and Design. 80-83 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Y.Yoshida, B.Y.Song, H.Okuhata, T.Onoye, and I.Shirakawa: "An Object Code Compression Approach to Embedded Processors" Proc.International Symposium on Low Power Electronics and Design. 265-268 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] M.Yamaguchi, A.Yamada, T.Nakaoka, T.Kambe and N.Ishiura: "Architecture Evaluation Based on the Datapath Structure and Parallel Constraint" IEICE Trans.Fundamentals of Electronics, Communications and Computer Sciences. vol.E80-A,no.10. 1853-1860 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] N.Ishiura, M.Yamaguchi: "Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning" Proc. of the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97). 105-109 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] M.Yamaguchi, N.Ishiura, and T.Kambe: "Binding and Scheduling Algorithms for Highly Retargetable Compilation" Proc. Asia and South Pacific Design Automation Conference (ASP-DAC '98). 93-98 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] T.Onoye, G.Fujita, H.Okuhata, M.H.Miki, and I.Shirakawa: "Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing" Proc. Asia and South Pacific Design Automation Conference (ASP-DAC '98). 589-594 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] K.Miyanohana: "VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication" Proc.IEEE Costom Integrated Circuits Conference. 229-232 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] G.Fujita: "A New Motion Estimation Core Dedicated to H.263 Video Coding" Proc.IEEE International Symposium on Circuits and Systems. 1161-1164 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] M.H.Miki: "Low-Power H.263 Video CoDec Dedicated to Mobile Computing" Proc.International Symposium on Low Power Electronics and Design. 80-83 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] T.Onoye: "Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing" Proc.Asia and South Pacific Design Automation Conference. 589-594 (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] M.Yamaguchi: "Architecture Evaluation Based on the Datapath Structure and Parallel Constraint" IEICE Trans. Fundamentals. E80-A,10. 1853-1860 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] M.Yamaguchi: "An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint" Proc.IEEE International Symposium on Circuits and Systems. 1584-1587 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] M.Yamaguchi: "Binding and Scheduling Algorithms for Highly Retargetable compilation" Proc.Asia and South Pacific Design Automation Conference. 93-98 (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] Y.Yoshida: "An Object Code Compression Approach to Embedded Processors" Proc.International Symposium on Low Power Electronics and Design. 265-268 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] N.Ishiura: "Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field partitioning" Proc.Workshop on Synthesis and System Integration of Mixed Technologies. 105-109 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] T.ONOUE I.SHIRAKAWA et al.: "single chip Irplerentation of Motion Estimator Dedicated to MPEG2 MPQHC" IEICE Trans.Fundapentals. E79A-8. 1210-1216 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] K.OKADA I.SHIRAKAWA et al.: "A High Perforrance Multiglrer and Its Application to on FIR Filter Pediated to Digital Video Transmission" IEICE Trans.Fundapentals. E79A-12. 2106-2111 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] S.NAKAMURA N.ISHIURA et al.: "High-Lecal Syrthosis System for Behaveioral Deseriptions with Conditional Brandet" Proc.ITC-CSCC. Vol.1. 935-938 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] Y.SHIGEHIRO I.SHIRAKAWA et al.: "A Fast Menerum Lost Flow Algoritha and Its Application to VCSI Layour Corpaction" Proc.ITC-CSCC. Vol.1. 951-954 (1996)

    • Related Report
      1996 Annual Research Report

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Published: 1996-04-01   Modified: 2016-04-21  

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