| Budget Amount *help |
¥4,200,000 (Direct Cost: ¥4,200,000)
Fiscal Year 1996: ¥4,200,000 (Direct Cost: ¥4,200,000)
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| Research Abstract |
Need for high robustness against hardware faults increases considerably in the future computers as the hardware sizes of them enlarge. The goal of this research is to propose the computers which have high robustness against faults happen in their run-time as well as in the fabrication process. In this research, neuro-computer is chosen as a target computer. High fault tolerance is expected in the neuro-computer because it mimics the biological neural system. However, not so many results have been repoted concerning its fault tolerance. Especially, the fault tolerance of SOM (Self-Organizing Map) which is one of the promising neuro-computer architectures has not been explored yet.
The autonomous repairing ability of the SOM has been evaluated theoretically and experimentally, using the real neuro-computer. The research conclusions are :
1) an extremely long pseudo stable state emerges because of the faulty neurons in the SOM.However, the global ordering state is achieved eventually after the pseudo stable state. A technique to shorten the pseudo stable state period has been proposed and its effectiveness has been analyzed quantitatively.
2) the critical-stuck-output rho_c of the defective neuron has been derived from the defect SOM model. If the defective neuron's output rho_d is much smaller than rho_c, the global-ordering state can hardly be achieved. However, the probability that this undesired case happens is about 6% of all stuck-outputs in the present neuro-computer.
3) Experiments on the defective SOM have been carried out, and the results have been well agreed with the above theoretical predictions, indicating that the theoretical evaluation is correct. The obtained results and criteria will be utilized for the future neuro-computers and fault-tolerant neuro-computers designs.
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