| Project/Area Number |
08458058
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Tohoku University |
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Principal Investigator |
HIGUCHI Tatsuo Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (20005317)
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| Co-Investigator(Kenkyū-buntansha) |
YUMINAKA Yasushi Gunma University, Faculty of Engineering Research Associate, 工学部, 助手 (30272272)
AOKI Takafumi Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院・情報科学研究科, 助教授 (80241529)
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| Project Period (FY) |
1996 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥8,500,000 (Direct Cost: ¥8,500,000)
Fiscal Year 1998: ¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 1997: ¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 1996: ¥3,400,000 (Direct Cost: ¥3,400,000)
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| Keywords | Multiple- Valued Logic / Set- Valued Logic / Logic Circuits / Integrated Circuits / Opto-Electronic Integrated Circuits / Molecular Devices / Molecular Computing |
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| Research Abstract |
In this project, we investigated a potential of "multiplex computing architectures" (listed below) to address interconnection problems in advanced VLSI systems.
1. [Multiple-Valued Logic System] New arithmetic computing architectures using non-binary/high-radix number systems, such as high-radix dividers, a high-radix CORDIC processor, a redundant complex multiplier and reconfigurable arithmetic datapaths, were developed to demonstrate advantages of improving processing latency, circuit complexity, gate count and power consumption. Also, the impact of multiple-valued integrated circuit technology was investigated through experimental fabrication.
2. [FDMA/CDMA-Based Computing Architectures] Set-valued logic architectures based on FDMA (Frequency-Division Multiple Access) and CDMA (Code-Division Multiple Access) were investigated. A test chip for ODMA-based set-valued logic was fabricated using current-mode CMOS to demonstrate significant reduction in wiring complexity. Also, flexible control of bit error rate in intra-chip data transmission is possible by controlling the length of M-sequence codes and the degree of multiplexing. This idea was also extended to the design of wire-efficient neural network architectures.
3. [Multiwavelength Optical Interconnection] A multiwavelength optical interconnection network for MCM-based parallel processing was proposed and its key device the "wavelength detector" was developed. It was shown that the wavelength detector can discriminate 8 16 wavelengths multiplexed within a waveguide and that this degree of multiplexing makes possible the reduction of network area complexity by the factor of 1/64 - 1/256 in comparison with a single wavelength implementation.
4. [Molecular Computing System] A molecular computing architecture using "enzyme transistors" was investigated. The basic function of an enzyme transistor was confirmed experimentally.
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