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A Research on a Virtual Model-Architecture for Massively Parallel Computer Systems

Research Project

Project/Area Number 08458069
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionKyoto Institute of Technology

Principal Investigator

SHIBAYAMA Kiyoshi  Kyoto Inst.Tech., Eng. & Design, Prof., 工芸学部, 教授 (70127091)

Co-Investigator(Kenkyū-buntansha) HIRATA Hiroaki  Kyoto Inst.Tech., Eng. & Design, Assistant Prof., 工芸学部, 助手 (90273549)
NIIMI Haruo  Kyoto Inst.Tech., Eng. & Design, Assoc.Prof., 工芸学部, 助教授 (40144331)
Project Period (FY) 1996 – 1997
Project Status Completed (Fiscal Year 1997)
Budget Amount *help
¥5,900,000 (Direct Cost: ¥5,900,000)
Fiscal Year 1997: ¥2,500,000 (Direct Cost: ¥2,500,000)
Fiscal Year 1996: ¥3,400,000 (Direct Cost: ¥3,400,000)
KeywordsMssively Parallel Computer System / Model-Architecture / Virtual computer / Testbed / Computer Architecture / Hardware / Software Tradeoffs
Research Abstract

On the side of the architects of massively parallel processors, it is difficult to manufacture by way of tried experiment and to access their own designing architectures repeatedly. Therefore, it is looked for an environment aiding to design and assess the hardware / software tradeoff.
And, though required the experimental environment for the consistent education from algorithm to system programming and hardware architecture, a few institution can provide a massively parallel processing system.
In this research, we have provided a virtual massively parallel processing environment aiming at effective use for education and research. We have summarized requirements for this environment, and emphasized its adaptability to various problems. We have suggested a virtual model-architecture, consisting of clusters of multiple bus-based distributed shared memory architecture. We have also discussed implementation of the virtual massively parallel processor architecture which is the kernel of this environment. Finally, we have presented an experimental parallel programming system.

Report

(3 results)
  • 1997 Annual Research Report   Final Research Report Summary
  • 1996 Annual Research Report
  • Research Products

    (18 results)

All Other

All Publications (18 results)

  • [Publications] 野中 恵三: "並列処理による重力多体問題の解法の高速化" 情報処理学会・研究報告. 97-HPC-65. 39-44 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 天津 克秀: "分散メモリ型並列計算機向き階層化スレッドスケジューリング方式" 電子情報通信学会・論文誌. J80-D-I-7. 615-623 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 平田 博章: "マルチスレッドプロセッサおよび1チップマルチプロセッサのための命令キャッシュ構成・命令フェッチ方式の性能評価" 電子情報通信学会・論文誌. J80-D-I-5(掲載予定). (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 柴山 潔: "ハードウェア入門" サイエンス社, 153 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Keizoh NONAKA: "To Speed up Gravitational N-body Problem Solving by Parallel Processing" IPSJ SIG Notes. 97-HPC-65. 39-44 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Katsuhide AMATSU: "Studies of Hierarchical Thread Scheduling for Distributed Memory Parallel Processors" Trans.IEICE. 180-D-I-7. 615-623 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Hiroaki, HIRATA: "Performance Comparisons of Instruction Cache Configurations and Instruction Fetch Schemes for a Multithreaded Processor or a 1-Chip Multiprocessor" Trans.IEICE. J81-D-I-5, (in print). (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] Kiyoshi SHIBAYAMA: Introduction to Computer Hardware. Saiensusha, 153 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1997 Final Research Report Summary
  • [Publications] 野中 恵三: "並列処理による重力多体問題の解法の高速化" 情報処理学会・研究報告. 97-HPC-65. 39-44 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] 天津 克秀: "分散メモリ型並列計算機向き階層化スレッドスケジューリング方式" 電子情報通信学会・論文誌. J80-D-I-7. 615-623 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] 平田 博章: "マルチスレッドプロセッサおよび1チップマルチプロセッサのための命令キャッシュ構成・命令フェッチ方式の性能評価" 電子情報通信学会・論文誌. J81-D-I-5(掲載予定). (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] 柴山 潔: "ハードウェア入門" サイエンス社, 153 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] 西野 秀昭: "並列オブジェクト指向システムにおけるオブジェクト管理方式" 電子情報通信学会・技術研究報告. CPSY96-40. 7-12 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 布目 淳: "多重階層化負荷管理方式による超並列計算機向き動的負荷分散" 電子情報通信学会・技術研究報告. CPAY96-30. 13-18 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 山村 周史: "並列処理によるMPEGエンコーダの高速化" 電子情報通信学会・技術研究報告. CPSY96-64. 55-62 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 下村 武: "超並列計算機向き相互結合網HXB/b-HCの提案" 電子情報通信学会・技術研究報告. CPSY96-50. 23-30 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 柴田 幸茂: "メッセージ駆動スレッド方式による要素プロセッサアーキテクチャMDT-1" 情報処理学会・研究報告. ARC-119-40. 233-238 (1996)

    • Related Report
      1996 Annual Research Report
  • [Publications] 柴山 潔: "コンピュータアーキテクチャ" オーム社, 416 (1997)

    • Related Report
      1996 Annual Research Report

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Published: 1996-04-01   Modified: 2016-04-21  

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