| Budget Amount *help |
¥2,500,000 (Direct Cost: ¥2,500,000)
Fiscal Year 1998: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1997: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 1996: ¥1,200,000 (Direct Cost: ¥1,200,000)
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| Research Abstract |
In this research, in 1996 and 1997
1)Combination of the analog hardware description language MAST-AHDL with the system ASSIST for development of circuit simulators, and development of the analog/digital mixed signal simulator SPADE,
2) Development of the multi-level simulator DESIRE which can cope with lumped/distributed elements-mixed circuits,
3)Development of a novel high-speed neural network simulator have been done. in 1998, the above researches has been continued and the following results have been obtained.
a)The analog hardware description language Verilog-Ahas been combined with ASSIST.As a result, we have constructed the system which enables modeling of the functional blocks by Verilog-A, where SPADE can simulate the mixed signal circuits
b)The expanded GMC has been proposed for the large scale interconnect network analysis. Furthermore, FDTD method has been combined with DESIRE.As a result, we have constructed the high performance simulator which can simulate efficiently linear/nonlinear large networks with many interconnects.
c) We have applied SPADE to the simulation of neural networks, where the operational amplifier and the neuron amplifier have been modeled by Verilog-A.As a result, we have confirmed that analog neural networks can be simulated efficiently by SPADE.
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