| Project/Area Number |
08650478
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計測・制御工学
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| Research Institution | IBARAKI UNIVERSITY |
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Principal Investigator |
MIYATA Takeo IBARAKI Univ.President, 学長 (10106742)
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| Co-Investigator(Kenkyū-buntansha) |
TSUKAMOTO Kosuke IBARAKI Univ.Fac.of Eng, Assistant Professor., 工学部, 講師 (90171975)
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| Project Period (FY) |
1996 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 1998: ¥200,000 (Direct Cost: ¥200,000)
Fiscal Year 1997: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1996: ¥1,400,000 (Direct Cost: ¥1,400,000)
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| Keywords | Redundant binary code / Adder / Multiplier / Flip Flop / CMOS / Symmetric Ternary / A / D converter / Plasma Display / MT-CMOS / A-D変換器 / 電流モード回路 / プラスマディスプレイ |
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| Research Abstract |
In order to develop a high-speed and high-accuracy signal processing system, new signal processing circuits using RBC(Redundant Binary Code) are proposed.
1. An RBC code converter based on the Modified Booth Algorithm is proposed. The multiplier using the code converter has the advantage of fast multiplying operation, because the number of partial products is reduced by the code converter.
2. To spread the use of the RBC signal processing system, RBC sequential logic circuits are proposed. The circuits can be optimized with the ternary-valued CMOS logic gates.
3. A construction method of RBC adder composed of multi-threshold CMOS(MT-CMOS) logic gates is proposed. A feature of the RBC adder is low power dissipation based on the MT-CMOS circuits.
4. The circuit design of an analog to RBC converter is proposed. The main advantage of the converter is error calibration based on the inherent redundancy of the RBC system.
5. The RBC system is applied to a driving method of plasma display panel. This driving method increases conventional two level gray scale to tree level gray scale using RBC, combining light emitting time and amplitude, and selecting driving waveform not to produce flicker.
The performance of the proposed circuits mentioned above are investigated by SPICE simulation and prototype test using the discrete components. As the results, the effectiveness of the proposed methods is confirmed.
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