| Project/Area Number |
08650505
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計測・制御工学
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| Research Institution | HACHINOHE INSTITUTE OF TECHNOLOGY05AA : 08650505 |
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Principal Investigator |
TOMABECHI Nobuhiro HACHINOHE INSTTUTE OF TECHNOCOGY, 工学部, 教授 (70048180)
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| Co-Investigator(Kenkyū-buntansha) |
FUJIOKA Yoshichika HACHINOHE INSTTUTE OF TECHNOCOGY, 工学部, 講師 (70275527)
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| Project Period (FY) |
1996 – 1997
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| Project Status |
Completed (Fiscal Year 1997)
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| Budget Amount *help |
¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 1997: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1996: ¥900,000 (Direct Cost: ¥900,000)
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| Keywords | REDUNDANCY / HIGHLY INTEGRATED / ROBOT / CONTROL / OROCESSOR / DESIGN / VLSI / 歩留り |
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| Research Abstract |
Analysis of the yield enhancement of WSI by introducibg redundancy (1)The effect of the hardware of the redundant interconnection lines and the exchanging switches Although the redundant interconnection lines and the exchanging switches essential for redundant structure, they are usually neglected in the yield analysis.This study analyzes the effect of the hardware on the yield enhancement of WSI.(2)2-dimensional sudsystem-dividing A redundancy design in which a system is divided into two directions is proposed.It is made clear that the yield of the target system can be enhanced by this desing.
Design of a highly integrated robot control processor In the preceding study.a processor element (PE)had been designed to be integrated on a VLSI chip In this study.a highly integrated processor composed 20-100 PEs is designed on a single wafer.The data transfer between PEs is designed to perform through the multiple buses so as to operate all of the fntegrated PE effectively at any time.An efficient design of the multiple buses characterized by the dynamic dividing is proposed.
Defect recovery of the highly integrated robot control processor The most difficult problem in realizing the highly integrated processor is decreased yield resulting from increased production defects.Against this study proposes a defect recovery desing in which the reonfigurable architecture of the processor is effectively utilised.It is found that a processor composed of PEs (84 PEs are effective) may be implemented on a single wafer.The application of the highly integrated processor to the robot control is also studied and it is found that the delay time in operation can be greatly reduced.
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