| Budget Amount *help |
¥2,500,000 (Direct Cost: ¥2,500,000)
Fiscal Year 1998: ¥100,000 (Direct Cost: ¥100,000)
Fiscal Year 1997: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 1996: ¥900,000 (Direct Cost: ¥900,000)
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| Research Abstract |
Multistage Interconnection Networks (MINs) have been researched for an interconnection network used in middle scale scientific multiprocessors, since multiple processors can access multiple memory modules simultaneously. However, coherent private cache mechanism is difficult to be implemented, and it is a reason why such types of multiprocessor has not been widely utilized.
In this research, a MIN with Cache coherent mechanism called MING is proposed, designed and implemented. Using a reduced hierarchical bit map directory method and pruning mechanism, MINC can manage coherent mechanism with a small additional hardware. Using the 0.6um LPGA(Laser Programmable Gate Array) technology, the designed MING chip(Network scale : 16-input/16-output) is implemented in a single chip(26477 cells including 6OKbit memory). The chip works with at least 50MHz clock, and the total throughput of the chip is 800Mbyte/sec(50Mbyte/sec for each port).
Using the MINC chip and a high speed switch called PBSF (Piled Banyan Switching Fabrics), a multiprocessor prototype called SNAIL-2 was designed and implemented. SNAIL-2, the first MIN-connected multiprocessor with a hardwired coherent cache mechanism, provides 16 processors/16 memory modules. A simple but high speed RISC (R3000) is adopted for a processor, and it can be used for evaluation of MING and PBSF chips with real parallel applications.
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