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MULTIPLE-VALUED PROCESSOR FOR INTELLIGENT INTEGRATED SYSTEM

Research Project

Project/Area Number 09044125
Research Category

Grant-in-Aid for international Scientific Research

Allocation TypeSingle-year Grants
SectionJoint Research
Research Field 計算機科学
Research InstitutionTOHOKU UNIVERSITY

Principal Investigator

HANYU Takahiro  Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院・情報科学研究科, 助教授 (40192702)

Co-Investigator(Kenkyū-buntansha) LIN H.C.  University of Maryland, Professor, 教授
NG Wai-Tung  University of Toronto, Faculty of Applied Science and Engineering, Professor, 応用科学工学部, 助教授
GULAK Glenn  University of Toronto, Faculty of Applied Science and Engineering, Professor, 応用科学工学部, 教授
SMITH Kenneth C.  University of Toronto, Faculty of Applied Science and Engineering, Professor, 応用科学工学部, 教授
KAMEYAMA Michitaka  Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (70124568)
NG Wai Tung  トロント大学, 助教授
SMITH Rennet  トロント大学, 教授
Project Period (FY) 1997 – 1998
Project Status Completed (Fiscal Year 1998)
Budget Amount *help
¥3,100,000 (Direct Cost: ¥3,100,000)
Fiscal Year 1998: ¥1,200,000 (Direct Cost: ¥1,200,000)
Fiscal Year 1997: ¥1,900,000 (Direct Cost: ¥1,900,000)
KeywordsMultiple-valued content-addressable memory (CAM) / Floating-gate-MOS pass-transistor network / Threshold operation / Logic-in-memory VLSI architecture / Non-numeric data processing / Fully parallel processing / Magnitude comparison / Intelligent information processing
Research Abstract

Real-world applications need to achieve very quick response for dynamically changing real-world environment. Therefore, it is very important to develop a "Super Chip for Intelligent Integrated Systems." The emerging technologies of intelligent integrated systems for real-world applications rely increasingly on VLSI processors high degree of parallelism in various levels such as architectural, logic design, and circuit/device level. The following items are the themes discussed in this project : (1)Discussion about algorithm/system/architecture-level innovation : We have discussed about the efficiency of multiple-valued logic-in-memory VLSI as the development of fully parallel image processor for intelligent integrated systems. The basic idea of the multiple-valued logic-in-memory VLSI architecture is that the data which are frequently used in the communication between the processing element (PE) and the memory are stored into the local memory tightly connected to the PE.We also discussed about the efficiency of some concrete examples using such concept.
(2)Discussion about logic-design/circuit-design-level innovation : We have presented a floating-gate-MOS pass-transistor network as a circuit-level logic-in-memory VLSI architecture. We have discussed about the usefulness of such a new pass-transistor network and about its application areas. While a floating-gate MOS transistor is used as a multiple-valued storage element in the present VLSI system, some logical functions such as a threshold function and a pass-switch function are merged into the multiple-valued memory plane.
(3)Discussion about device/process-technology-level innovation : We have also discussed about the device technologies to realize the floating-gate-MOS pass-transistor network.

Report

(3 results)
  • 1998 Annual Research Report   Final Research Report Summary
  • 1997 Annual Research Report
  • Research Products

    (74 results)

All Other

All Publications (74 results)

  • [Publications] T.Hanyu: "Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs" Proc.of 1999 IEEE International Symposium on Multiple-Valued Logic (to be published). 29. (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic" Proc.of 1999 IEEE International Symposium on Multiple-Valued Logic (to be published). 29. (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 堀井崇史: "処理要素間配線数の最小化に着目したロジックインメモリVLSI" 電子情報通信学会総合全国大会予稿集. 発表予定. (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 羽生貴弘: "2色2線符号化に基づく多値非同期VLSIシステムの構成" 電子情報通信学会総合全国大会予稿集. 発表予定. (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 杉山智宏: "2値論理合成CADを活用した多値VLSIシステムの自動設計" 電子情報通信学会総合全国大会予稿集. 発表予定. (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 木村啓明: "強誘電体キャパシタを用いた多値連想メモリVLSIの構成" 電子情報通信学会「多値論理とその応用」第2種研究会技術報告. MVL99. 53-60 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 羽生貴弘: "フローティングゲートMOSトランジスタを用いたユニバーサルリテラル形多値ロジックアレー" 多値論理研究ノート. 21. 12-1〜12-9 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 池 司: "2線式電流モード回路を用いたセルフチェッキング多値VLSIシステム" 多値論理研究ノート. 21. 11-1〜11-7 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 堀井崇史: "共通バス本数最小化に着目したロジックインメモリVLSIシステムの設計" 平成10年度電気関係学会東北支部連合大会予稿集. 319 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 羽生貴弘: "強誘電体多値連想メモリのアーキテクチャ" 平成10年度電気関係学会東北支部連合大会予稿集. 290 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 池 司: "セルフチェッキング機能を有するソース結合形電流モード多値論理システムの構成" 平成10年度電気関係学会東北支部連合大会予稿集. 315 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 工藤隆男: "ロジックインメモリアーキテクチャに基づく道路抽出VLSIプロセッサとその評価" 平成10年度電気関係学会東北支部連合大会予稿集. 314 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic" Proc.of 1998 IEEE International Symposium on Multiple-Valued Logic. 28. 134-139 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Multiple-Valued Floating-Gate-MOS Pass Logic and Its Application to Logic-in- Memory VLSI" Proc.of 1998 IEEE International Symposium on Multiple-Valued Logic. 28. 270-275 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 羽生貴弘: "フローティングゲートMOSトランジスタを用いた多値ロジックインメモリVLSIの構成" 電子情報通信学会集積回路研究会技術報告. ICD98ー36. 1-8 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 羽生貴弘: "2線式電流モード多値集積回路を用いた非同期プロセッサの構成" 電子情報通信学会集積回路研究会技術報告. ICD97-228. 1-8 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 齋藤敬弘: "電流モードディープサブミクロン多値集積回路の最適設計とその応用" 電子情報通信学会和文論文誌D-I. J81-D-I,2. 157-164 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 羽生貴弘: "ディジットパラレル多値CAMの構成と評価" 電子情報通信学会和文論文誌D-I. J81-D-I,2. 151-156 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Multiple-Valued Logic-Memory VLSI Based on a Floating-Gate-MOS Pass-Transistor Networks" Dig.of 1998 IEEE International Solid-State Circuits Conference. 41. 194-195 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 與那嶺尚弘: "Morphology画像処理用多値VLSIプロセッサの構成" 電子情報通信学会「多値論理とその応用」第2種研究会技術報告. MVL98. 74-83 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Non-Volatile One-Transistor-Cell Multiple-Valued CAM with a Digit-Parallel- Access Scheme and Its Applications" Computers Elect.Eng.23,6. 407-414 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 齋藤敬弘: "電流モードディープサブミクロン多値集積回路の最適設計" 平成9年度電気関係学会東北支部連合大会予稿集. 42 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 寺西 要: "パスゲート論理に基づくディジットパラレル多値連想メモリの設計" 平成9年度電気関係学会東北支部連合大会予稿集. 41 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing" IEICE Trans.Electron.E80-C,7. 948-955 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control" IEICE Trans.Electron.E80-C,7. 941-947 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 羽生貴弘: "NAND構造4値ユニバーサルリテラルCAMとその応用" 多値論理研究ノート. 20. 5-1〜5-10 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing" Proc.of 1997 IEEE International Symposium on Multiple-Valued Logic. 27. 175-180 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Multiple-Valued Contnet-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs" Proc.of 1999 IEEE International Symposium on Multiple-Valued Logic (to be published). 29. (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic" Proc.of 1999 IEEE International Symposium on Multiple-Valued Logic (to be published). 29. (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Horii: "High-Level Synthesis of a Logic-in-Memory VLSI System with the Minimum Number of Shared Buses" Proc.of the 1999 IEICE General Conference (to be published). (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Design of a Miltiple-Valued Asynchronous VLSI System Based on Two-Color Two-Rail Coding" Proc.of the 1999 IEICE General Conference (to be published). (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Sugiyama: "Automated Design of a Miltiple-Valued VLSI System Using a Binary Logic Synthesis CAD" Proc.of the 1999 IEICE General Conference (to be published). (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] H.Kimura: "Miltiple-Valued Contnet-Addressable Memory VLSI Using Ferroelectric Capacitors" MVL Technical Report of IEICE. MVL-99. 53--60 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Universal-Literal-Type Miltiple-Valued Logic Array Using Floating-Gate MOS Transistors" Note on Miltiple-Valued Logic in Japan. 21. 12-1-12-9 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Ike: "Self-Checking Multiple-Valued VLSI System Using Dual-Rail Current-Mode Logic Circuits" Note on Miltiple-Valued Logic in Japan. 21. 11-1-11-7 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic" Proc.of 1998 IEEE International Symposium on Multiple-Valued Logic. 28. 134-139 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Multiple-Valued Floating-Gate-MOS Passl Logic and Its Application to Logic-in-Memory VLSI" Proc.of 1998 IEEE International Symposium on Multiple-Valued Logic. 28. 270-275 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Design of a Multiple-Valued Logic-in-Memory VLSI Using Floating-Gate-MOS Transistors" Integrated Circuits and Devices, Technical Report of the IEICE. ICD98-36. 1-8 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Design of an Asynchronous Processor Using Dual-Rail Multiple-Valued Current-Mode Integrated Circuits" Integrated Circuits and Devices, Technical Report of the IEICE. ICD97-228. 1-8 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Saito: "Optical Design of a Current-Mode Deep-Submicron Multiple-Valued Integrated Circuit and Its Application" Trans.On IEICE D-I. J81-D-I,2. 157-164 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Design and Evaluation of a Digit-Parallel Multipul-Valued Content-Addressable Memory" Trans.On IEICE D-I. J81-D-I,2. 151-156 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Multipul-Valued Logic-in-Memory VLSI Based on a Floating-Gate-MOS Pass-Transistor Networks" Dig.of 1998 IEEE International Solid-State Circuits Conference. 41. 194-195 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Yonamine: "Design of a Multiple-Valued VLSI Processor for Morphological Image Processing" MVL Technical Report of the IEICE. MVL-98. 74-83 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Non-Volatile One-Transistor-Cell Multiple-Valued CAM with a Digit-Parallel-Access Scheme and Its Applications" Computers Elect.Eng.23,6. 407-414 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing" IEICE Trans.Electron.E80-C,7. 948-955 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control" IEICE Trans.Electron.E80-C,7. 941-947 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "4-Valued Universal-Literal CAM Based on NAND Structure and Its Applications" Note on Multiple-Valued Logic in Japan. 20. 5-1-5-10 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] T.Hanyu: "One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing" Proc.of 1997 IEEE International Symposium on Multiple-Valued Logic. 27. 175-180 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 羽生貴弘: "フローティングゲートMOSトランジスタを用いた多値ロジックインメモリVLSIの構成" 電子情報通信学会技術報告. ICD98-36. 1-8 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] T.Hanyu: "Multiple-Valued Floating-Gate-MOS Pass Logic and Its Application to Logic-in-Memory VLSI" Proc.of 1998 IEEE International Symposium on Maltiple-Nolued Logic. 28. 270-275 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] T.Hanyu: "Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic" Proc.of 1998 IEEE International Symposium on Maltiple-Volued Logic. 28. 134-13* (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 池 司: "セルフチェッキング機能を有するソース結合形電流モード多値論理システムの構成" 平成10年度電気関係学会東北支部連合大会予稿集. 315 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 工藤隆男: "ロジックインメモリアーキテクチャに基づく道路抽出VLSIプロセッサとその評価" 平成10年度電気関係学会東北支部連合大会予稿集. 314 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 羽生貴弘: "強誘電体多値連想メモリのアーキテクチャ" 平成10年度電気関係学会東北支部連合大会予稿集. 290 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 堀井崇史: "共通バス本数最小化に着目したロジックインメモリVLSIシステムの設計" 平成10年度電気関係学会東北支部連合大会予稿集. 319 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 池 司: "2線式電流モード回路を用いたセルフチェッキング多値VLSIシステム" 多値論理研究ノート. 21. 11-1,11-7 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 羽生貴弘: "フローティングゲートMOSトランジスタを用いたユニバーサルリテラル形多値ロジックアレー" 多値論理研究ノート. 21. 12-1,12-9 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 木村啓明: "強誘電体キャパシタを用いた多値連想メモリVLSIの構成" 電子情報通信学会「多値論理とその応用」研究会技術報告. MVL99. 53-60 (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] 羽生貴弘: "2色2線符号化に基づく多値非同期VLSIシステムの構成" 電子情報通信学会総合全国大会予稿集. (発表予定). (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] 堀井崇史: "処理要素間配線数の最小化に着目したロジックインメモリVLSI" 電子情報通信学会総合全国大会予稿集. (発表予定). (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] T.Hanyu: "Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs" Proc.of 1999 IEEE International Symposium on HuHiple-Valued Logic. 29(to be published). (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] T.Hanyu: "Self-Checking Multiple-Valued Circuit Based on Dual-Rail Corrent-Mode Differential Logic" Proc.of 1999 IEEE International Symposium on Hultiple-Valued Logic. 29(to be published). (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] T. Hanyu: "One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing" Proc. of IEEE 27th International Symposium on Multiple-Valued Logic. 27. 175-180 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] M. Hariyama: "Collision Detection VLSI Processor for Intelligent Vehicles Based on a Hierarchical Obstacle Representation" IEEE Conterence on Intelligent Transportation Systems. (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] 張山 昌論: "高安全自動車用軌道計画VLSIプロセッサシステムの構成" 電子情報通信学会フォールトトレラントコンピューティング研究会. (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] T. Hanyu: "Design and Evaluation of a 4-Valued Universal-Literal CAM for Collular Logic Image Recessing" IEICE Trans. Electronics. E80-C・7. 948-955 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] 寺西 要: "パスゲート論理に基づくディジットパラレル多値連想メモリの設計" 平成9年度電気関係学会東北支部連合大会予稿集. 41 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] 佐々木 和宏: "階層的直方体表現に基づく衝突チェックVLSIプロセッサの構成" 平成9年度電気関係学会東北支部連合大会予稿集. 228 (1997)

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  • [Publications] M. Hariyama: "Path Planning VLSI Processor System for Intelligent Vehicles" 第15回日本ロボット学会学術講演会予稿集. 1025-1026 (1997)

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  • [Publications] T. Hanyu: "Multiple-Valued Logic-in-Memory VSLI Based on a Floating-Gate-Mos Pass-Transistor Network" 1998 Digest of IEEE International Solid-State Circuits Conterence. 41. 194-195 (1998)

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  • [Publications] 羽生 貴弘: "ディジットパラレル多値CAMの構成と評価" 電子情報通信学会和文誌DI. J81-DI-2. 151-156 (1998)

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  • [Publications] T. Hanyu: "Multiple-Valued Floating-Gate-MOS Pass Logic and Its Application to Logic-in-Memory VLSI" Proc. of IEEE 28th International Symposium on Multipk-Valued Logic(掲載決定). 28. (1998)

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  • [Publications] 斉藤 敬弘: "ディープサブミクロン多値集積回路の最適設計" 平成9年度電気関係学会東北支部連合大会予稿集. 42 (1997)

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  • [Publications] 斉藤 敬弘: "電流モードディープサブミクロン多値集積回路の最適設計とその応用" 電子情報通信学会和文誌DI. J81-DI・2. 157-164 (1998)

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Published: 1997-04-01   Modified: 2016-04-21  

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