| Project/Area Number |
09305023
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (A)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
電子デバイス・機器工学
|
|---|
| Research Institution | TOHOKU UNIVERSITY |
|---|
Principal Investigator |
KOYANAGI Mitsumasa Graduate School of Engineering, Tohoku University, Professor, 大学院・工学研究科, 教授 (60205531)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
KURINO Hiroyuki Graduate School of Engineering, Tohoku University, Assistant Professor, 大学院・工学研究科, 講師 (70282093)
HANE Kazuhiro Graduate School of Engineering, Tohoku University, Professor, 大学院・工学研究科, 教授 (50164893)
ESASHI Masayoshi New Industry Creation Hatchery Center, Tohoku University, Professor, 未来科学技術共同研究センター, 教授 (20108468)
柳 基鎬 東北大学, 大学院・工学研究科, 助手 (20270811)
|
|---|
| Project Period (FY) |
1997 – 1999
|
| Project Status |
Completed (Fiscal Year 1999)
|
| Budget Amount *help |
¥37,100,000 (Direct Cost: ¥37,100,000)
Fiscal Year 1999: ¥4,600,000 (Direct Cost: ¥4,600,000)
Fiscal Year 1998: ¥11,500,000 (Direct Cost: ¥11,500,000)
Fiscal Year 1997: ¥21,000,000 (Direct Cost: ¥21,000,000)
|
|---|
| Keywords | IMAGE PROCESSING / REAL-TIME / LEARNING / ASSOCIATION / NEURAL NETWORK / PARALLEL PROCESSING / 3D INTEGRATION / WAFER BONDING / 三次元積層技術 |
|---|
| Research Abstract |
We have proposed a new image processing chip with three-dimensional structure. This chip consists of four layers of image sensor array, amplifier and AD converter array, resister (data latch) array and processor array. These four layers are connected vertically using high density of vertical interconnections. Therefore, 2D image signal data are simultaneously transferred in vertical direction and processed in parallel in each layer. In order to transfer the 2D output data from this chip to other chips with high speed and high efficiency, the 2D output data are compressed and reconstructed using a neural network. It was confirmed that the learning and association function of neural network is useful for the data compression and reconstruction. We have developed a new 3D integration technology to realize such image processing chip with learning and association function. In this 3D integration technology, the device wafer with the buried interconnections are glued to a quartz glass and then thinned from the back side using the mechanical grinding and CMP. The micro bumps are formed on the bottom of the buried interconnections at the back side. This thinned device wafer is glued to the another device wafer after a careful wafer alignment. By repeating this sequence, the 3D stacked wafer is obtained. We fabricated the 3D stacked image sensor test chip using this 3D integration technology. The electrical characteristics of this stacked 3D image sensor test chip were evaluated through the buried interconnections and micro bumps.
|
