Grant-in-Aid for Scientific Research (A)
|Allocation Type||Single-year Grants |
|Research Institution||KYUSHU UNIVERSITY |
MURAKAMI Kazuaki Grad. School of ISEE, Kyushu University, Associate Professor, 大学院・システム情報科学研究科, 助教授 (10200263)
MIYAZAKI Akio Grad. School of ISEE, Kyushu University, Associate Professor, 大学院・システム情報科学研究科, 助教授 (70192763)
TANIGUCHI Hideo Grad. School of ISEE, Kyushu University, Associate Professor, 大学院・システム情報科学研究科, 助教授 (70253507)
YASUURA Hiroto Grad. School of ISEE, Kyushu University, Professor, 大学院・システム情報科学研究科, 教授 (80135540)
SAWADA Sunao Grad. School of ISEE, Kyushu University, Research Associate, 大学院・システム情報科学研究科, 助手 (70235464)
IWAIHARA Mizuho Grad. School of ISEE, Kyushu University, Associate Professor, 大学院・システム情報科学研究科, 助教授 (40253538)
松岡 聡 東京工業大学, 大学院情報理工学研究科, 助教授 (20221583)
|Project Period (FY)
1997 – 1999
Completed (Fiscal Year 1999)
|Budget Amount *help
¥28,600,000 (Direct Cost: ¥28,600,000)
Fiscal Year 1999: ¥5,400,000 (Direct Cost: ¥5,400,000)
Fiscal Year 1998: ¥12,000,000 (Direct Cost: ¥12,000,000)
Fiscal Year 1997: ¥11,200,000 (Direct Cost: ¥11,200,000)
|Keywords||merged memory / logic / system LSI / parallel / distributed processing / inter-LSI interconnect / low power circuit / computer architecture / cache memory / computational science / メモリ・ロジック混載 / 並列・分散処理 / 性能評価 / 大規模集積回路|
The objectives of this research project are to develop system-LSI architectures and computer-system architectures, or PPRAM (Parallel Processing RAM), which are based mainly on merged memory/logic technology, parallel/distributed processing technology , and inter-LSI high-speed interconnect technology. The project has performed the following research results.
(1) Inter-LSI high-speed interconnect standard, or PPRAM-Link : The project has defined a set of specifications for physical layer, logical layer, and API of PPRAM-Link ; and then it has implemented these specifications in several ways.
(2) Reference PPRAM architectures : The project has developed a couple of architectures good for merged DRAM/logic system-LSI, such as (I) shared-register CMP (chip multiprocessor), (ii) statically/dynamically variable line-size cache, (iii) way-predicting set-associative cache.
(3) DRAM refresh architectures for merged DRAM/logic LSI : The project has developed a couple of architectures good for merg
ed DRAM/logic system-LSI so that alleviate the DRAM refresh characteristics to be worsened by on-chip logic.
(4) Hardware/software codesign methodology for embedded system-LSI : The project has developed a hardware/software codesign methodology based on soft-core processor and Valen-C technologies.
(5) Software-controlled low power architectures : The project has designed a processor architecture, or PowerPro, which can optimize the power consumption by means of software control according to the system load.
(6) Test methodology for system-LSI : The project has proposed a test methodology good for system-LSI, which combines BIST and external test.
(7) PPRAM-based MOE (molecular orbital calculation engine) : The project has developed some PPRAM applications, including MOE chips and MOE system. The MOE chip consists of a 32-bit integer RISC processor, a 76-bit MO-specific floating-point processor, 1Mb SRAM, and a PPRAM-Link interface. The MOE system consists of a number of MOE boards, each of which includes five MOE chips and a bridge chip for PPRAM-Link and IEEE1394.
(8) PPRAM-based realtime digital-watermarking engine for movies : Another PPRAM application is a realtime digital-watermarking engine for movies. The project has implemented a suite of wavelet transformation function, PPRAM-Link interface and PCI-bus interface by means of FPGA. Less