| Project/Area Number |
09450135
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Tohoku University |
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Principal Investigator |
NAKAJIMA Koji Research Institute of Electrical Communication, Tohoku University, Professor, 電気通信研究所, 教授 (60125622)
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| Co-Investigator(Kenkyū-buntansha) |
ONOMI Takeshi Research Institute of Electrical Communication, Tohoku University, Research Associate, 電気通信研究所, 助手 (70312676)
SATO Shigeo Research Institute of Electrical Communication, Tohoku University, Research Associate, 電気通信研究所, 助手 (10282013)
水柿 義直 東北大学, 電気通信研究所, 助手 (30280887)
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| Project Period (FY) |
1997 – 1999
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| Project Status |
Completed (Fiscal Year 1999)
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| Budget Amount *help |
¥13,400,000 (Direct Cost: ¥13,400,000)
Fiscal Year 1999: ¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 1998: ¥3,300,000 (Direct Cost: ¥3,300,000)
Fiscal Year 1997: ¥6,600,000 (Direct Cost: ¥6,600,000)
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| Keywords | Neural Network / Dynamic Memory / Neuro Chip / Integrated Circuit / Chaos / Limit Cycle / Non-monotonic Neuron / Associative Memory / 時系列情報 / 層状回路 / カオス集積回路 |
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| Research Abstract |
The purposes of this research are analyses for behaviors of neuro-based dynamic memories, research for applications of the memories, a constitution of the memory, analyses for learning ability of the memories, a hardware integration of the memories aimed at real time processings. We analyzed the number of limit cycles generated in a single neural network by using a proposed learning algorithm. We also analyzed the characteristics of the limit cycles and transition states to the limit cycles, and characteristics of a non-monotonic neuron network which has a higher performance of learning ability. Interactions among the limit cycles, initial states, and chaotic noise were investigated on fabricated neuro-chips with integrated chaotic signal generators. In order to investigate dynamic behaviors of quantized interconnection networks on neuro-chips, we have designed and fabricated a hardware neural network according to the design rule of a CMOS technology. The 225 (and 42) full connections between 15 (and 7) neurons and the self-couplings can be performed in the fabricated neuro-chip. The number of limit cycles which can be produced on the single network increases sharply with increasing the number of neurons in case of nearest neighbor connections. For an example, 1.14x10ィイD17ィエD1 limit cycles in the case of 40 neurons are estimated at least. The limit cycles have basins of attraction, and hence, we may utilize the network as associative memeory to retrieve dynamical cyclic patterns. We also presented the quantized interconnection network to solve the N-parity problem and a random Boolean function with arbitrary N inputs. Finally, we discussed the learning possibility for the quantized interconnection networks. These results show the high performance of the neuro-based dynamic memories and the high possibility of applications of the memory as intelligent information processors.
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