| Project/Area Number |
09450144
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
電子デバイス・機器工学
|
|---|
| Research Institution | Hiroshima University |
|---|
Principal Investigator |
MATTAUSCH Hans J. Res. Center for Nanodev. and Systems, Hiroshima University, Professor, ナノデバイス・システム研究センター, 教授 (20291487)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
NAGATA Makoto Faculty of Engineering, Hiroshima University, Research Associate, 工学部, 助手 (40274138)
IWATA Atsushi Faculty of Engineering, Hiroshima University, Professor, 工学部, 教授 (30263734)
YOKOYAMA Shin Res. Center for Nanodev. and Systems, Hiroshima University, Professor, ナノデバイス・システム研究センター, 教授 (80144880)
|
|---|
| Project Period (FY) |
1997 – 1999
|
| Project Status |
Completed (Fiscal Year 1999)
|
| Budget Amount *help |
¥13,300,000 (Direct Cost: ¥13,300,000)
Fiscal Year 1999: ¥2,600,000 (Direct Cost: ¥2,600,000)
Fiscal Year 1998: ¥7,600,000 (Direct Cost: ¥7,600,000)
Fiscal Year 1997: ¥3,100,000 (Direct Cost: ¥3,100,000)
|
|---|
| Keywords | Common Memory / Multiport Memory / Copy Bus / Access Conflict / Hierarch. Architecture / Electro-optical Integration |
|---|
| Research Abstract |
The purpose of this research project was to find a new high-bandwidth common memory architecture, which substantially advances the state of the art in this field, so that high-bandwidth common memories become applicable in practice. A special question was, whether electro-optical integration, with signal transmission by light over optical wave-guides, is necessary for achieving this aim.
The main result of the project is the development and verification of a new area-efficient hierarchical multiport-memory architecture. This architecture enables genuine common memories with large storage capacities and terabit-per-second access bandwidth in practice. Terabit-per-second access bandwidth becomes possible by the implementation of ,up to 32 ports with independent and parallel access capability. Both area-efficiency and access-bandwidth can be improved by an order of magnitude in comparison to the previous state of the art. The access-bandwidth increases approximately proportional to the port-number. The area-reduction factors have been investigated quantitatively for the case of the SRAM. They amount to <1/2, <1/5, <1/14 and <1/30 for the cases of 4, 8, 16 and 32 ports, respectively.
Electro-optical integration is not necessary for achieving this technological breakthrough. For even higher bandwidth and more than 32 ports, we have developed a new copybus common-memory architecture, which then is expected to need signal transmission by light over optical wave-guides for realizing the necessary high throughput of the copybusses.
|
