• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Study on Asynchronous VLSI System Design Methodology

Research Project

Project/Area Number 09480049
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionThe University of Tokyo

Principal Investigator

NANYA Takashi  Research Center for Advanced Science and Technology, The University of Tokyo, Professor, 先端科学技術研究センター, 教授 (80143684)

Co-Investigator(Kenkyū-buntansha) UENO Yoichiro  Faculty of Engineering, Tokyo Denki University, Assistant Professor, 工学部, 講師 (70262285)
KUWAKO Masashi  Research Center for Advanced Science and Technology, The University of Tokyo, Assistant, 先端科学技術研究センター, 助手 (20292766)
NAKAMURA Hiroshi  Research Center for Advanced Science and Technology, The University of Tokyo, Associate Professor, 先端科学技術研究センター, 助教授 (20212102)
Project Period (FY) 1997 – 1999
Project Status Completed (Fiscal Year 1999)
Budget Amount *help
¥12,400,000 (Direct Cost: ¥12,400,000)
Fiscal Year 1999: ¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 1998: ¥4,800,000 (Direct Cost: ¥4,800,000)
Fiscal Year 1997: ¥5,500,000 (Direct Cost: ¥5,500,000)
KeywordsAsynchronous Processor / Asynchronous Circuits / Asynchronous VLSI system / VLSI system design / Asynchronous Logic Design / Asynchronous Circuit Testing / VLSI設計 / マイクロプロセッサ / アーキテクチャ / 論理設計
Research Abstract

We established a design methodology to support the synthesis of high-performance and large-scale asynchronous systems. The main results of this research project are described below.
(1) The speed-performance and power consumption of the asynchronous, processor TITAC-2 was evaluated. Based on the evaluation results, we defined a design strategy that speeds up an asynchronous pipeline and improves the power-performance ratio.
(2) We did the RTL design of the asynchronous superscalar processor TITAC-3 in order to develop, and evaluate the defined asynchronous systems design methodology. The "cascade ALU" method, which provides a higher parallelism in instruction execution than traditional superscalar synchronous processors, was defined and adopted in TITAC-3 design. Our simulation results indicate that TITAC-3 can achieve IPC=1.90 and 258MIPS of performance.
(3) The fine-grain-pipelining method was proposed, implemented and evaluated. This method takes advantage of the unique characteristics … More of DCVSL (Differential Cascode Voltage Switch Logic) circuits in order to conceal the idle-phase and controller delays. The implementation of high-speed arithmetic circuits was clarified. We proposed, implemented, and evaluated a method that adds completion-signal generation circuit to arithmetic circuits based on the SDI model.
(4) We proposed and evaluated a method that synthesizes high-speed controllers from STG (Signal Transition Graph) by adding appropriate ordering relation to the graph in order to solve CSC, conflict (Complete-State-Coding conflict). Also, a method to synthesize high-speed controllers by adding ordering relations, which are based on the delay properties of the controlled data path circuit, to an STG was proposed and evaluated.
(5) An online test technique using BICS (Built-In Current Sensor) that reduces the influence of premature completion signals (a peculiar problem of asynchronous circuits) was proposed.
(6) A technique to realize pulse logic (which uses signal pulses as an information carrier) asynchronous data path circuits was proposed. Less

Report

(4 results)
  • 1999 Annual Research Report   Final Research Report Summary
  • 1998 Annual Research Report
  • 1997 Annual Research Report
  • Research Products

    (70 results)

All Other

All Publications (70 results)

  • [Publications] M. Maezawa: "Rapid single -flux-quantum dual-rail logic for asynchronous circuits."IEEE Transactions on Applied Superconductivity. Vol7 No2. 2705-2708 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Akihiro Takamura: "TITAC-2 : An asynchronous 32-bit microprocessor based on scalable-delay-insensitive model"Proc. International Conf. Computer Design. 288-294 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 籠谷裕人: "同期式回路スケジューリング法に基づいた非同期式回路設計のための依存性グラフ作成法"電子情報通信学会論文誌A. J82-A No2. 239-246 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 今井雅: "SDIモデルに基づいた非同期式パイプライン・データパスの論理合成"情報処理学会論文誌. Vol40 No4. 1547-1556 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Yoshio Kameda: "Self-timed parallel adders based on DI RSFQ primitives"IEEE Trans. On Applied Superconductivity. Vol9 No2. 4040-4045 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 亀田義男: "パルス論理による非同期式データパス回路の構成"電子情報通信学会論文誌. J83-D-I No1. 1-8 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 南谷崇: "非同期式VLSI設計"情処研報. Vol97-ARC126. 19-24 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 今井雅: "配線遅延を考慮した非同期式加算回路の性能評価"信学技報. FTS97-2. 9-16 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 小沢基一: "非同期式プロセッサTITAC-2の性能解析"情処研報. ARC97-102. 103-108 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 上野洋一郎: "非同期式プロセッサを用いたコンピュータシステムの実現"情処研報. ARC97-102. 109-114 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 桑子雅史: "データパスの特性を考慮した非同期式制御回路の一設計手法"情処研報. ARC97-102. 115-120 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 小沢基一: "非同期式パイプライン構造の性能評価"信学技報. ICD98-18. 53-60 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 上野洋一郎: "非同期式カスケードALUアーキテクチャ"信学技報. ICD98-19. 61-68 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 今井雅: "DCVSLを利用した非同期式細粒度パイプライン・データパスの論理合成"信学技報. CPSY98-87. 47-54 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 中野栄治: "SD符合を用いた非同期式高速除算器"信学技報. CPS99-9. 21-28 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 小沢基一: "細粒度化による非同期式パイプラインの最適化設計"信学技報. CPSY99-10. 29-36 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 藤木崇宏: "非同期式プロセッサTITAC-3の命令供給機構"情処研報. ARC99-133. 1-6 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 小沢基一: "Cascade ALUを用いた命令実行手法の提案と評価"情処研報. ARC99-133. (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 今井雅: "2線式ドミノ論理による細粒度パイプライン・データパスの性能比較"信学技報. CPSY99-93. 73-80 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] B. R. Kishore: "A mixed-signal approach for on-line testing of asynchronous circuits - a case study"Proceedings of 3rd IEEE International On-line Testing Workshop. 91-95 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takashi Nanya: "TITAC-2:A 32-bit scalable-delay-insensitive microprocessor"Symposium Record of HOT Chips IX. 19-32 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Mohit Sahni: "On the CSC property of signal transition graph specifications for asynchronous circuit design"Proc. Of Asia and South Pacific Design automation Conference. 183-189 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Akihiro Takanura: "TITAC-2: An asynchronous 32-bit microprocessor"ASP-DAC. 319-320 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Yoshio Kameda: "Primitive-level pipelining method on delay-insensitive model for RSFQ pulse-driven logic"international Symposium on Advanced Research in Asynchronous Circuits and Systems. 262-273 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takashi Nanya: "Asynchronous microprocessor architecture and design"Proc. FED-PDI Joint Confrence on 21th Century Electron Devices. (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takashi Nanya: "Scalable-delay-insensitive design: A high-performance approach to dependable asynchronous systems"International Symposium on Future of Intellectual Integrated Electronics. 531-540 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] M. Maezawa: "Rapid single-flux-quantum dual-rail logic for asynchronous circuits."IEEE Transactions on Applied Superconductivity. Vol. 7, No. 2. 2705-2708 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Akihiro Takamura: "FITAC-2 : An asynchronous 32-bit microprocessor based on scalable-delay-insensitive model"Proc. International Conf. Computer Design. 288-294 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Hiroto Kagotani: "Composition of Dependency Graphs for A Circuit Synthesis based on Synchronous Circuit scheduling"The Trans, of the Institute of Electronics, Information and Communication Engineerings,. J82-A No. 2. 239-246 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Masashi Imai: "Logic Synthesis of Pipelined Asynchronous Data-paths Based on the SDI Model"Transactions of Information Processing Society of Japan. Vol. 40 No. 4. 1547-1556 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Yoshio Kameda: "Self-timed parallel adders based on DI RSFQ primitives"IEEE Trans. on Applied Superconductivity. Vol. 9 No. 2. 4040-4045 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Yoshio Kameda: "Pulse-Driven Asynchronous Data Path Structure"The Trans of the Institute of Electronics, Information and Communication Engineerings. J83-D-I No. 1. 1-8 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] B. R. Kishore: "A mixed-signal approach for on-line testing of asynchronous circuits - a case study"Proceedings of 3rd IEEE International Online Testing Workshop. 91-95 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takashi Nanya: "TITAC-2 A 32-bit scalable-delay-insensitive micro processor"Symposium Record of HOT Chips IX. 19-32 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Mohit Sahni: "On the CSC property of signal transition graph specifications for asynchronous circuit design"Proc. of Asia and South Pacific Design Automation Conference. 183-189 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Akihiro Takamura: "TITAC-2 An asynchronous 32-bit microprocessor"ASP-DAC. 319-320 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Yoshio Kameda: "Primitive-level pipelining method on delay-insensitive model for RSFQ pulse-driven logic"International Symposium on Advanced Research in Asynchronous Circuits and Systems. 262-273 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takashi Nanya: "Asynchronous microprocessor architecture and design"Proc. FED-PEI Joint Conference on 21th Century Electron Devices. (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takashi Nanya: "Scalable-delay-insensitive design : A high-performance approach to dependable asynchronous systems"International Symposium on Future of Intellectual Integrated Electronics. 531-540 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takashi Nanya: "Asynchronous VLSI Systems Design"Technical Report of IPSJ. Vol. 97-ARC126. 19-24 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Masashi Imai: "Asynchronous VLSI Systems Design"Technical Report of IPSJ. FTS97-2. 9-16 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Motokazu Ozawa: "Performance Analysis for Asynchronous Processor TITAC-2"Technical Report of IPSJ. ARC97-102. 103-108 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Yoichiro Ueno: "Implementation of A Computer System with An Asynchronous Processor"Technical Report of IPSJ. ARC97-102. 109-114 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Masashi Kuwako: "A design method for asynchronous controllers using data-path delay information"Technical Report of IPSJ. ARC97-102. 115-120 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Motokazu Ozawa: "Performance Evaluation for Asynchronous Pipeline Structure"Technical Report of IEICE. ICD98-18. 53-60 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Yoichiro Ueno: "Asynchronous Cascade ALU Architecture"Technical Report of IEICE. ICD98-19. 61-68 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Masashi Imai: "Logic synthesis of finely pipelined asynchronous data-paths using DCVSL cells"Technical Report of IEICE. CPSY98-87. 47-54 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Eiji Nakano: "Fast Asynchronous Nonrestoring Division with Singed Digit Representation"Technical Report of IEICE. CPSY99-9. 21-28 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Motokazu Ozawa: "A Design Optimization Method for Fine-grained Asynchronous Pipeline"Technical Report of IEICE. CPSY99-10. 29-36 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Fujiki: "Instruction Issue Mechanism for Asynchronous Processor TITAC-3"Technical Report of IPSJ. ARC99-133. 1-6 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Motokazu Ozawa: "Instruction Execution Mechanism based on Cascade ALU"Technical Report of IPSJ. ARC99-133. (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Masashi Imai: "Performance Comparison of Finely Pipelined Data-paths using Differential Domino Logic"Technical Report of IEICE. CPSY99-93. 73-80 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 今井、中村、南谷: "SDIモデルに基づいた非同期式パイプライン・データパスの論理合成"情報処理学会論文誌. Vol.40,No.4. 1547-1556 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Y. Kameda, S. V. Polonsky, M. Maezawa, T. Nanya: "Self-timed parallel adders based on DI RSFQ primitives"IEEE Trans. on Applied Superconductivity. Vol.9,No.2. 4040-4045 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 亀田、南谷: "パルス論理による非同期式データパス回路の構成"電子情報通信学会論文誌. VolJ83-D1.,No.2. 1-8 (2000)

    • Related Report
      1999 Annual Research Report
  • [Publications] 籠谷、岡本、南谷: "同期式回路スケジューリング法に基づいた非同期式回路設計のための依存性グラフ作成法" 電子情報通信学会論文誌A. Vol.J82-A,No.2. 239-246 (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] 今井、中村、南谷: "SDIモデルに基づいた非同期式パイプライン・データパスの論理合成" 情報処理学会論文誌. Vol.40,No.4(掲載予定). (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] Y.Kameda,S.V.Polonsky,M.Maezawa,T.Nanya: "Self-timed parallel adders based on DI RSFQ primitives" to appear in IEEE Trans.on Applied Superconductivity. (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] Takashi Nanya: "Asynchronous microprocessor architecture and design(invited paper)" Proc.FED-PDI Joint Confrence on 21th Century Electron Devices(FPC'98). (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] T.Nanya,他: "Scalable-Delay-Insensitive Design:A high-performance approachto dependable asynchronous systems(Invited paper)" Proc.International Symp.on Future of Intellectual Integrated Electronics,Sendai. (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] 南谷 崇: "微細化進行に配線遅延の壁" 電子ジャーナル. 1998年5月号. 19 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 南谷、今井、小沢: "非同期技術の潮流と実践のアプローチ" エレクトロニクス. Vol.43,No.8. 65-74 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 南谷 崇: "非同期式プロセッサTITAC-2の開発" 電子情報通信学会誌. Vol.81,No.8. 821-829 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 南谷 崇: "非同期式コンピュータ" Computer Today. No.89. 25-30 (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] B.R.Kishore, Y.Kameda,T.Nanya: "A mixed-signal approach for on-line testing of asynchronous circuits-a case study" Proc.3rd IEEE International On-line Testing Workshop. 91-95 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] Akihiro Takamura, Takashi Nanya 他: "TITAC-2:A 32-bit Asynchronous Microprocessor based on Scalable-Delay-Insensitive Model" Proc.ICCD'97. 288-294 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] M.Sahni and T.Nanya: "On the CSC property of signal transition graph specifications for asynchronous circuit design(Best Paper Award)" Proc.ASP-DAC. 183-189 (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] A.Takamura, T.Nanya 他: "TITAC-2:An asynchronous 32-bit microprocessor(Outstanding Design Award)" Proc.ASP-DAC. 319-320 (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] Y.Kameda, T.Nanya 他: "Primitive-level pipelining method on delay-insensitive model for RSFQ pulse-driven logic" to appear at ASYNC-98. (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] 南谷 崇: "非同期式マイクロプロセッサの動向" 情報処理. Vol.39,No.3. (1998)

    • Related Report
      1997 Annual Research Report

URL: 

Published: 1997-04-01   Modified: 2016-04-21  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi