| Project/Area Number |
09480049
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | The University of Tokyo |
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Principal Investigator |
NANYA Takashi Research Center for Advanced Science and Technology, The University of Tokyo, Professor, 先端科学技術研究センター, 教授 (80143684)
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| Co-Investigator(Kenkyū-buntansha) |
UENO Yoichiro Faculty of Engineering, Tokyo Denki University, Assistant Professor, 工学部, 講師 (70262285)
KUWAKO Masashi Research Center for Advanced Science and Technology, The University of Tokyo, Assistant, 先端科学技術研究センター, 助手 (20292766)
NAKAMURA Hiroshi Research Center for Advanced Science and Technology, The University of Tokyo, Associate Professor, 先端科学技術研究センター, 助教授 (20212102)
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| Project Period (FY) |
1997 – 1999
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| Project Status |
Completed (Fiscal Year 1999)
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| Budget Amount *help |
¥12,400,000 (Direct Cost: ¥12,400,000)
Fiscal Year 1999: ¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 1998: ¥4,800,000 (Direct Cost: ¥4,800,000)
Fiscal Year 1997: ¥5,500,000 (Direct Cost: ¥5,500,000)
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| Keywords | Asynchronous Processor / Asynchronous Circuits / Asynchronous VLSI system / VLSI system design / Asynchronous Logic Design / Asynchronous Circuit Testing / VLSI設計 / マイクロプロセッサ / アーキテクチャ / 論理設計 |
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| Research Abstract |
We established a design methodology to support the synthesis of high-performance and large-scale asynchronous systems. The main results of this research project are described below.
(1) The speed-performance and power consumption of the asynchronous, processor TITAC-2 was evaluated. Based on the evaluation results, we defined a design strategy that speeds up an asynchronous pipeline and improves the power-performance ratio.
(2) We did the RTL design of the asynchronous superscalar processor TITAC-3 in order to develop, and evaluate the defined asynchronous systems design methodology. The "cascade ALU" method, which provides a higher parallelism in instruction execution than traditional superscalar synchronous processors, was defined and adopted in TITAC-3 design. Our simulation results indicate that TITAC-3 can achieve IPC=1.90 and 258MIPS of performance.
(3) The fine-grain-pipelining method was proposed, implemented and evaluated. This method takes advantage of the unique characteristics
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of DCVSL (Differential Cascode Voltage Switch Logic) circuits in order to conceal the idle-phase and controller delays. The implementation of high-speed arithmetic circuits was clarified. We proposed, implemented, and evaluated a method that adds completion-signal generation circuit to arithmetic circuits based on the SDI model.
(4) We proposed and evaluated a method that synthesizes high-speed controllers from STG (Signal Transition Graph) by adding appropriate ordering relation to the graph in order to solve CSC, conflict (Complete-State-Coding conflict). Also, a method to synthesize high-speed controllers by adding ordering relations, which are based on the delay properties of the controlled data path circuit, to an STG was proposed and evaluated.
(5) An online test technique using BICS (Built-In Current Sensor) that reduces the influence of premature completion signals (a peculiar problem of asynchronous circuits) was proposed.
(6) A technique to realize pulse logic (which uses signal pulses as an information carrier) asynchronous data path circuits was proposed. Less
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