| Project/Area Number |
09480051
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
計算機科学
|
|---|
| Research Institution | Japan Advanced Institute of Science and Technology |
|---|
Principal Investigator |
HORIGUCHI Susumu Japan Advanced Institute of Science and Technology, Information Science, Professor, 情報科学研究科, 教授 (60143012)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
INOGUCHI Yasushi Japan Advanced Institute of Science and Technology, Information Center, Research Associate, 情報科学研究科, 助手 (90293406)
HAYASHI Ryouko Japan Advanced Institute of Science and Technology, Information Science, Research Associate, 情報科学研究科, 助手 (30303332)
YAMAMORI Kunihito Japan Advanced Institute of Science and Technology, Information Science, Research Associate, 情報科学研究科, 助手 (50293395)
TAKEDA Hirokatu Yamagata University, Research Associate, 工学部, 助手 (90236472)
|
|---|
| Project Period (FY) |
1997 – 1999
|
| Project Status |
Completed (Fiscal Year 1999)
|
| Budget Amount *help |
¥5,100,000 (Direct Cost: ¥5,100,000)
Fiscal Year 1999: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1998: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1997: ¥3,100,000 (Direct Cost: ¥3,100,000)
|
|---|
| Keywords | VLSI, ULSI / VLSI Reconfiguration / Massively Computer / 3D-Stacked Wafers / Hierarchical Network / Routing / 階層型相互結合網 / ウェーハ積層構造型 / 超並列ネットワーク / 超並列計算機システム / フォールトトレランス性能 / ウェーハ間結 / 超並列コンピュータ / ウェーハ積層構造 / 再帰シフトトーラス結合綱SRT / 自律再構成方式 |
|---|
| Research Abstract |
With the continuing advances in VLSI technology, multiprocessor systems with tens to hundreds of processing elements are expected to rival today's supercomputers in the next decade. Systems consisting of a few tens to a million processing elements have indeed been described in the literature. The development of such large scale systems will make numerous applications such as multi-media, computer vision, and modeling of physical phenomena to be feasible on desk-top workstations. However, a major issue in designing large scale multiprocessor systems is the construction of a flexible interconnection network to provide efficient inter-processor communication.
This research develops a hierarchically structured interconnection network, 'Tori connected mESHes' (TESH), which allows exploitation of computational locality as well as modular future expansion. Also, the network has reduced wiring and only a few ports per processor, features that are essential in cost-effective implementation of large scale computing systems. Further, it has a regular structure which makes addressing of nodes and message routing rather straightforward. The network also appears to permit 3-D stacked implementation. In part, this is due to the far fewer number of vertical wires needed than almost all known multi-computer networks. As is well known, parallelizing a problem is usually application-specific and system architecture dependent. Therefore, several applications such as sorting, merging, FFT, and convolution, have been mapped to the network as paradigms in.
|
