| Project/Area Number |
09480057
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | KYUSHU UNIVERSITY |
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Principal Investigator |
YASUURA Hiroto Graduate School of Inf.Sci.and Elec.Eng., KYUSHU UNIVERSITY,Professor, 大学院・システム情報科学研究科, 教授 (80135540)
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| Co-Investigator(Kenkyū-buntansha) |
ISHIHARA Tohru Graduate School of Inf.Sci.and Elec.Eng., KYUSHU UNIVERSITY,JSPS Research Fellow, 大学院・システム情報科学研究科, 日本学術振興会特別研
TOMIYAMA Hiroyuki Graduate School of Inf.Sci.and Elec.Eng., KYUSHU UNIVERSITY,JSPS Research Fellow, 大学院・システム情報科学研究科, 日本学術振興会特別研
SAWADA Sunao Graduate School of Inf.Sci.and Elec.Eng., KYUSHU UNIVERSITY,Instructor, 大学院・システム情報科学研究科, 助手 (70235464)
IWAIHARA Mizuho Graduate School of Inf.Sci.and Elec.Eng., KYUSHU UNIVERSITY,Associate Professor, 大学院・システム情報科学研究科, 助教授 (40253538)
MURAKAMI Kazuaki Graduate School of Inf.Sci.and Elec.Eng., KYUSHU UNIVERSITY,Associate Professor, 大学院・システム情報科学研究科, 助教授 (10200263)
冨山 宏之 九州大学, 大学院システム情報科学研究科, 日本学術振興会特別研
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| Project Period (FY) |
1997 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥13,100,000 (Direct Cost: ¥13,100,000)
Fiscal Year 1998: ¥4,900,000 (Direct Cost: ¥4,900,000)
Fiscal Year 1997: ¥8,200,000 (Direct Cost: ¥8,200,000)
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| Keywords | low-power design / microprocessor systems / system LSI / variable voltage processor / logic-DRAM mixed LSI / logic synthesis / hardware-software codesign / DRAM / ロジック混載LSI / 低消費電力 / マイクロプロセッサ / 論理設計 / アーキテクチャ / コンパイラ / 命令スケジューリング / データパス幅 / 組み込みシステム |
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| Research Abstract |
We proposed novel design techniques for low-power consumption microprocessor systems utilizing characteristics of LSIs. The research covers low-power architectures of processors and memories, an optimum control strategy of supply voltage for minimizing power consumption, and hardware/software codesign techniques for low-power design. The following results have been obtained.
1) Development of low-power systems with a variable voltage processor architecture : In this architecture, we provide several supply voltage levels and clock frequency corresponding to each voltage level. Programmers can select the optimum voltage levels according to the required load of programs. We proved a basic theorem for the selection of the optimum voltage and implemented a prototype processor with a voltage control instruction. More than 70% power reduction is achieved for practical programs.
2) Development of a low-power processor with variable data-path width : We proposed a new processor architecture in which active data-path width can be controlled from programs. This architecture can be easily combined with the hardware/software codesign technique based on Soft-core processor.
3) A compiler technique for reducing bus transitions and a low-power design technique of cache memories : We proposed a compiler technique which controls coding and order of transfer of instructions and data on buses. We also developed a power reduction method in which instructions and data read from cache memory are expected.
4) A low-power architecture of logic-DRAM mixed LSIs : For the memory hierarchy of logic-DRAM mixed LSI, we have proposed a. technique to reduce the number of refresh of DRAM to minimize the power consumption in the memory system.
5) Development of logic synthesis method for low-power circuits : We developed a new logic synthesis algorithm combined with Transduction method to generate the power minimum combinational circuits.
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