Research and Development for Analog-Digital Merged Image Processing
| Project/Area Number |
09555110
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | HIROSHIMA UNIVERSITY |
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Principal Investigator |
IWATA Atsushi Hiroshima University, Faculty of Engineering, Professor, 工学部, 教授 (30263734)
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| Co-Investigator(Kenkyū-buntansha) |
NAGATUMA Tadao NTT,Systemelectronics Research Center, Chief researcher, システムエレクトロニクス研究所, 主任研究員
NAGATA Makoto Hiroshima University, Faculty of Engineering, Assistant, 工学部, 助手 (40274138)
YOKOYAMA Shin Hiroshima University, Research Center for Nanodvices-Systems, Professor, ナノデバイス・システム研究センター, 教授 (80144880)
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| Project Period (FY) |
1997 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥11,400,000 (Direct Cost: ¥11,400,000)
Fiscal Year 1998: ¥5,200,000 (Direct Cost: ¥5,200,000)
Fiscal Year 1997: ¥6,200,000 (Direct Cost: ¥6,200,000)
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| Keywords | image processing LSI / PWM signals / signal processing circuit / pattern recognition / image sensor / 機能イメージセンサー / 信号検出処理回路 / WAC / WDC / 機能イメージセンサ |
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| Research Abstract |
In order to realize pattern recognition systems which extract features from two dimensional image data, the bio-inspired system architecture and low power circuit technique are proposed. A new image processing LSI chip is developed based on the proposed techniques. Merged analog-digital circuit architecture using pulse width modulation signals realizes parallel processing with low power and small chip area. Two dimensional image sensor array which senses image data, converts them to PWM signals and calculates' global features. A test chip was designed and fabricated with a O.8um double-poly, double-metal CMOS technology. The image sensor array with 64 x 64 pixels, an addressing circuit and a signal processing circuit for focal plane signal processing, are integrated on a l5 x l5mm chip. Experimental results shows the test chip realizes the feature detections and operates at 3.3V supply with low power dissipation. This techniques are expected effectivelly applied to recognition systems for characters, objects and faces, highly flexible vision systems for robots, and sensing system for various kinds of security systems.
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Report
(3 results)
Research Products
(14 results)
