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Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications

Research Project

Project/Area Number 09558025
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 計算機科学
Research InstitutionTOHOKU UNIVERSITY

Principal Investigator

KAMEYAMA Michitaka  Graduate School of Information Sciences, Tohoku University, Professor, 大学院・情報科学研究科, 教授 (70124568)

Co-Investigator(Kenkyū-buntansha) HARIYAMA Masanori  Graduate School of Information Sciences, Tohoku University, Research Associate, 大学院・情報科学研究科, 助手 (10292260)
HANYU Takahiro  Graduate School of Information Sciences, Tohoku University, Associate Professor, 大学院・情報科学研究科, 助教授 (40192702)
Project Period (FY) 1997 – 1999
Project Status Completed (Fiscal Year 1999)
Budget Amount *help
¥8,400,000 (Direct Cost: ¥8,400,000)
Fiscal Year 1999: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 1998: ¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 1997: ¥3,100,000 (Direct Cost: ¥3,100,000)
KeywordsDual-Rail Current-Mode Multiple-Valued Integrated Circuit / Logic-In-Memory VLSI / Self Checking Circuit / Highly-Parallel Arithmetic and Logic Circuit / Asynchronous Multiple-Valued VLSI / Reed-Muller Expansion / Partition Theory / 分割理論 / 非同期式多値演算回路 / 電流モード多値集積回路 / 電流源制御 / 非同期多値演算回路 / 低消費電力多値集積回路 / 電力源制御
Research Abstract

In this study, hardware algorithms for highly parallel arithmetic circuits, logic-in-memory VLSI architecture, and low-power, high-speed multiple-valued integrated circuits are considered in detail. The usefulness of the multiple-valued integrated circuits based on level multiplexing is established, and we can develop fundamental technology of a multiple-valued chip family. The major results of this research are shown below:
1. Design of highly-parallel multiple-valued arithmetic and logic circuits
The following three method are proposed to find code assignment for ultimately parallel multiple-valued operation circuits. When a functional specification of a k-ary operation is given by mapping relationship between input and output symbols. (1) Reed-Muller expansion by a sparse matrix, (2) Partion theory, and (3) Hierarchical code assignment using hot codes etc.
2. Development of current-mode multiple-valued integrated circuits
The use of a differential logic circuit with a pair of dual-rail … More inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage. The optimal circuit design is further considered to improve the performance with lower power dissipation. It is made clear that the use of two supply voltages is very useful for the improvement. Moreover, we developed asynchronous and self-checking design methods for the multiple-valued VLSI. As a result, we can obtain fundamental technology for the next-generation multiple-valued VLSI system.
3. Development of logic-in-memory multiple-valued VLSI system
A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. A multiple-valued sorted data is represented by a threshold voltage of the floating-gate-MOS transistor, so that a single floating-gate MOS transistor is effectively employed for merging a threshold-literal and a pass-switch function. As a typical example of the logic-in-memory VLSI, a fully parallel magnitude compartor is developed. The performance of the proposed VLSI is about 26 times higher than that of a corresponding binary implementation. Moreover, its effective chip area and power dissipation are reduced to about 42% and 20%, respectively. Less

Report

(4 results)
  • 1999 Annual Research Report   Final Research Report Summary
  • 1998 Annual Research Report
  • 1997 Annual Research Report
  • Research Products

    (65 results)

All Other

All Publications (65 results)

  • [Publications] Takahiro Hanyu: "Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control"Trans.IEICE. E80-C. 941-947 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Design and Evaluation of a 4-valued Universal-Literal CAM for Cellular Logic Image Processing"Trans.IEICE. E80-C. 948-955 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 霜觸謙介: "行列変換に基づくReed-Muller展開と高性能論理演算回路への応用"電子情報通信学会論文誌 D-I. J81-D-I. 126-132 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 羽生貴弘: "ディジットパラレル多値きCAMの構成と評価"電子情報通信学会論文誌 D-I. J81-D-I. 151-156 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 斎藤敬弘: "電流モードディープサブミクロン多値集積回路の最適設計とその応用"電子情報通信学会論文誌 D-I. J81-D-I. 157-164 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Non-Volatile One-Transistor-Cell Multiple-Valued CAM with a Digit-Parallel-Access Scheme and Its Applications"Computers & Electrical Engineering. Vol.23. 407-414 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Logic-in-Memory VLSI Based on Floating-Gate-MOS Pass-Transistor Logic"IEICE Trans. Electron.. E82-C. 1662-1668 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing"IEEE Proceedings of The Twenty-Seventh International Symposium on Multiple-Valued Logic. 175-180 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Logic-in-Memory VLSI Based on Floating-Gate-MOS Pass-Transistor Network"1998 IEEE International Solid-State Circuits Conference, Digest of Technical Papers. Vol.41. 194-195 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic"IEEE Proceedings of The Twenty-Eighth International Symposium on Multiple-Valued Logic. 134-139 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Floating-Gate-MOS Pass Logic and Its Application to Logic-in-Memory-VLSI"IEEE Proceedings of The Twenty-Eighth International Symposium on Multiple-Valued Logic. 270-275 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Michitaka Kameyama: "Innovation of Intelligent Integrated System Architecture"International Symposium on Future of Intellectual Integrated Electronics. 231-247 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs"IEEE Proceedings of The Twenty-Ninth International Symposium on Multiple-Valued. 30-35 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Self-Cheking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic"IEEE Proceedings of The Twenty-Ninth International Symposium on Multiple-Valued. 275-279 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 羽生貴弘: "2線式電流モード多値集積回路を用いた非同期プロセッサの構成"電子情報通信学会 技術報告資料. VLD97-123,ICD97-228. 1-8 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 羽生貴弘: "フローティングゲートMOSトランジスタを用いた多値ロジックインメモリVLSIの構成"電子情報通信学会 技術報告資料. ICD9836,FTS98-36. 1-8 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 羽生貴弘: "フローティングゲートMOSトランジスタを用いたユニバーサルリテラル形多値ロジックアレー"多値論理研究ノート. Vol.21. 1-9 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 池司: "2線式電流モード回路を用いたセルフチェッキング多値VLSIシステム"多値論理研究ノート. Vol.21. 1-7 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Michitaka Kameyama: "Construction of Intelligent Integrated Systems Based on New Concepts"17th Symposium on Future Electron Devices. 41-46 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 木村啓明: "強誘電体キャパシタを用いた多値連想メモリVLSIの構成"電子情報通信学会第2種研究会. (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] S.Kaeriyama: "Design of Multiple-Valued Logic-in-Memory VLSI Based on Linear Summation"Proc. 1st Korea-Japan Joint Symposium on MVL. 211-218 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 羽生貴弘: "2色2線符号化に基づく非同期電流モード多値VLSIシステム"電子情報通信学会技術報告資料. ICD99-166. 41-47 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control"Trans. IEICE. E80-C. 941-947 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Design and Evaluation of a 4-valued Universal-Literal CAM for Cellular Logic Image Processing"Trans. IEICE. E80-C. 948-955 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Kensuke Shimohure: "Reed-Muller Expansion Based on Matrix Transformation and Its Application to High-Performance Logic Circuits"Trans. IEICE. J81-D-I. 126-132 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Design and Evaluation of a Digit-Parallel Multiple-Valued Content-Addressable Memory"Trans. IEICE. J81-D-I. 151-156 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Optimal Design of a Current-Mode Deep-Submicron Multiple-Valued Circuit and Its Application"Trans. IEICE. J81-D-I. 157-164 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Non-Volatile One-Transistor-Cell Multiple-Valued CAM with a Digit-Parallel-Access Scheme and Its Applications"Computers & Electrical Engineering. Vol.23. 407-414 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Logic-in-Memory VLSI Based on Floating-Gate-MOS Pass-Transistor Logic"IEICE Trans. Electron.. E82-C. 1662-1668 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing"IEEE Proceedings of The Twenty-Seventh International Symposium on Multiple-Valued Logic. 175-180 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Logic-in-Memory VLSI Based on Floating-Gate-MOS Pass-Transistor Network"1998 IEEE International Solid-State Circuits Conference, Digest of Technical Papers. Vol.41. 194-195 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic"IEEE Proceedings of The Twenty-Eighth International Symposium on Multiple-Valued Logic. 134-139 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Floating-Gate-MOS Pass Logic and Its Application to Logic-in-Memory VLSI"IEEE Proceedings of The Twenty-Eighth International Symposium on Multiple-Valued Logic. 270-275 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Michitaka Kameyama: "Innovation of Intelligent Integrated System Architecture"International Symposium on Future of Intellectual Integrated Electronics. 231-247 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs"IEEE Proceedings of The Twenty-Ninth International Symposium on Multiple-Valued Logic. 30-35 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic"IEEE Proceedings of The Twenty-Ninth International Symposium on Multiple-Valued Logic. 275-279 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Design of an Asynchronous Processor Using Dual-Rail Multiple-Valued Current-Mode Integrated Circuits"Technical Report of IEICE. VLD97-123, ICD97-228. 1-8 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Design of a Multiple-Valued Logic-In-Memory VLSI Using Floating-Gate MOS Transistors"Technical Report of IEICE. ICD98-36, FTS98-36. 1-8 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Universal-Literal-Type Multiple-Valued Logic Array Using Floating-Gate MOS Transistors"Note on Multiple-Valued Logic in Japan. 21. 1-9 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Tsukasa Ike: "Self-Checking Multiple-Valued VLSI System Using Dual-Rail Current-Mode Logic Circuits"Note on Multiple-Valued Logic in Japan. 21. 1-7 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Michitaka Kameyama: "Construction of Intelligent Integrated Systems Based on New Concepts"17th Symposium on Future Electron Devices. November4-5. 41-46 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Hiromitsu Kimura: "Multiple-Valued Content-Addressable VLSI Using Ferroelectric Capacitors"MVL Technical Report of IEICE. MVL99. 53-60 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] S. Kaeriyama: "Design of Multiple-Valued Logic-in-Memory VLSI Based on Linear Summation"Proc. 1st Korea-Japan Joint Symposium on MVL. 211-218 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu: "Asynchronous Current-Mode Multiple-Valued VLSI System Based on Two-Color Two-Rail Coding"Technical Report of IEICE. ICD99-09. 41-47 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Takahiro Hanyu and Michitaka Kameyama: "Multiple-Valued Logic-in-Memory VLSI Based on Floating-Gate-MOS Pass-Transistor Logic"IEICE Trans.Electron.. Vol.E82-C No.9. 1662-1668 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Michitaka Kameyama,Takahiro Hanyu and Masanori Hariyama: "Innovation of Intelligent Integrated System Architecture"International Symposium on Future of Intellcetual Integrated Electronics. 231-247 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Takahiro Hanyu,Hiromitsu Kimura and Michitaka Kameyama: "Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs"IEEE Proceedings of The Twenty-Ninth International Symposium on Multiple-Valued Logic. 30-35 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Takahiro Hanyu,Tsukasa Ike and Michitaka Kameyama: "Self-Cheking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic"IEEE Proceedings of The Twenty-Ninth International Symposium on Multiple-Valued Logic. 275-279 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] S.Kameyama,T.Hanyu and M.Kameyama: "Design of Multiple-Valued Logic-in-Memory VLSI Based on Linear Summation"Proc. 1st Korea-Japan Joint Symposium On MVL. 211-218 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 羽生貴弘,亀山充隆: "2色2線符号化に基づく非同期電流モード多値VLSIシステム"電子情報通信学会技術報告資料. ICD99-166. 41-47 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 杉山智弘,羽生貴弘,亀山充隆: "2値論理合成CADを活用した多値 VLSIシステムの自動設計"電子情報通信学会総合大会(春季). A-3-4. (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 羽生貴弘,亀山充隆: "2色2線符号化に基づく多値非同期 VLSIシステムの構成"電子情報通信学会総合大会(春季). C-12-26. (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 羽生貴弘,亀山充隆: "2色2線符号化に基づく多値非同期 VLSIシステムの構成"電子情報通信学会総合大会(春季). C-12-26. (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 帰山隼一,羽生貴弘,亀山充隆: "ロジックインメモリ構造に基づく最小パターンマッチング VLSI""電気関係学会東北支部連合大会. 2H14. (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] T.Hanyu,T.Saito,M.Kameyama: "Asynchronous Multiple-Valued VISI System Based on Dual-Rail Current-Mode Differential Logic" IEEE Proc.The 28th International Symposium on Multiple-Valued Logic. 134-139 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] Michitaka Kameyama: "Construction of Intelligent Integrated Systems Based on New Concepts" 17th Symposium on Future Electron Devices. 41-46 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 池 司,羽生 貴弘,亀山 充隆: "セルフチェッキング機能を有するソース結合形電流モード多値論理システムの構成" 平成10年度電気関係学会東北支部連合大会. 315 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 池司,羽生貴弘,亀山充隆: "2線式電流モード回路を用いたセルフチェッキング多値VLSIシステム" 多値論理研究ノート. Vol.21,No.11. 1-7 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] T.Hanyu, S.Kazama and M.Kameyama: "Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuite with Current-Source Control." IEICE Trans.Electron.Vol.E80-C No.7. 941-947 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] T.Hanyu, M.Arakaki and M.Kameyama: "Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing" IEICE Trans.Electron.vol.E80-C No.7. 948-955 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] T.Hanyu, M.Arakaki and M.Kameyama: "One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing" Proc.of the 1997 IEEE International Symposium on Multiple-Valued Logic. 175-180 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] T.Hanyu, K.Teranishi and M.Kameyama: "Multiple-Valued Logic-in-Memory VLSI Based on a Flating-Gate-MOS Pass-Transistor Network" Technical Digest of 1998 IEEE International Solid State Circuits Conference. 194-195,437 (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] 斉藤, 羽生, 亀山: "電流モードディープサブミクロン多値集積回路の最適設計とその応用" 電子情報通信学会論文誌D-I. Vol.J81-D-I No.2. (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] 羽生, 寺西, 亀山: "ディジットパラレル多値CAMの構成と評価" 電子情報通信学会論文誌D-I. Vol.J81-D-I No.2. (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] 霜触、亀山: "行列変換に基づくReed-Muller展開と高性能論理演算回路への応用" 電子情報通信学会論文誌D-I. Vol.J81-D-I No.2. (1998)

    • Related Report
      1997 Annual Research Report

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Published: 1997-04-01   Modified: 2016-04-21  

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