| Project/Area Number |
09558025
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
計算機科学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
KAMEYAMA Michitaka Graduate School of Information Sciences, Tohoku University, Professor, 大学院・情報科学研究科, 教授 (70124568)
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| Co-Investigator(Kenkyū-buntansha) |
HARIYAMA Masanori Graduate School of Information Sciences, Tohoku University, Research Associate, 大学院・情報科学研究科, 助手 (10292260)
HANYU Takahiro Graduate School of Information Sciences, Tohoku University, Associate Professor, 大学院・情報科学研究科, 助教授 (40192702)
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| Project Period (FY) |
1997 – 1999
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| Project Status |
Completed (Fiscal Year 1999)
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| Budget Amount *help |
¥8,400,000 (Direct Cost: ¥8,400,000)
Fiscal Year 1999: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 1998: ¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 1997: ¥3,100,000 (Direct Cost: ¥3,100,000)
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| Keywords | Dual-Rail Current-Mode Multiple-Valued Integrated Circuit / Logic-In-Memory VLSI / Self Checking Circuit / Highly-Parallel Arithmetic and Logic Circuit / Asynchronous Multiple-Valued VLSI / Reed-Muller Expansion / Partition Theory / 分割理論 / 非同期式多値演算回路 / 電流モード多値集積回路 / 電流源制御 / 非同期多値演算回路 / 低消費電力多値集積回路 / 電力源制御 |
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| Research Abstract |
In this study, hardware algorithms for highly parallel arithmetic circuits, logic-in-memory VLSI architecture, and low-power, high-speed multiple-valued integrated circuits are considered in detail. The usefulness of the multiple-valued integrated circuits based on level multiplexing is established, and we can develop fundamental technology of a multiple-valued chip family. The major results of this research are shown below:
1. Design of highly-parallel multiple-valued arithmetic and logic circuits
The following three method are proposed to find code assignment for ultimately parallel multiple-valued operation circuits. When a functional specification of a k-ary operation is given by mapping relationship between input and output symbols. (1) Reed-Muller expansion by a sparse matrix, (2) Partion theory, and (3) Hierarchical code assignment using hot codes etc.
2. Development of current-mode multiple-valued integrated circuits
The use of a differential logic circuit with a pair of dual-rail
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inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage. The optimal circuit design is further considered to improve the performance with lower power dissipation. It is made clear that the use of two supply voltages is very useful for the improvement. Moreover, we developed asynchronous and self-checking design methods for the multiple-valued VLSI. As a result, we can obtain fundamental technology for the next-generation multiple-valued VLSI system.
3. Development of logic-in-memory multiple-valued VLSI system
A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. A multiple-valued sorted data is represented by a threshold voltage of the floating-gate-MOS transistor, so that a single floating-gate MOS transistor is effectively employed for merging a threshold-literal and a pass-switch function. As a typical example of the logic-in-memory VLSI, a fully parallel magnitude compartor is developed. The performance of the proposed VLSI is about 26 times higher than that of a corresponding binary implementation. Moreover, its effective chip area and power dissipation are reduced to about 42% and 20%, respectively. Less
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