| Project/Area Number |
09558027
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| Research Category |
Grant-in-Aid for Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
計算機科学
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| Research Institution | Tohoku Univesity |
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Principal Investigator |
HANYU Takahiro Tohoku Unniversity, Graduate School of Information Sciences, Associate Professor, 大学院・情報科学研究科, 助教授 (40192702)
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| Co-Investigator(Kenkyū-buntansha) |
KAMEYAMA Michitaka Tohoku Unniversity, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (70124568)
張山 昌論 東北大学, 大学院・情報科学研究科, 助手 (10292260)
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| Project Period (FY) |
1997 – 2000
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| Project Status |
Completed (Fiscal Year 2000)
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| Budget Amount *help |
¥11,700,000 (Direct Cost: ¥11,700,000)
Fiscal Year 2000: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1999: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 1998: ¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 1997: ¥6,700,000 (Direct Cost: ¥6,700,000)
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| Keywords | Multiple-Valued CAM / Floating-Gate MOS Transistor / Threshold Operation / Logic-in-Memory Architecture / Non-numeric Data Processing / Highly-Parallel Operation / Magnitude Comparison / Intelligent Information Processing / フローティングゲートMOSトランジスタ |
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| Research Abstract |
Communication bottleneck between memory and logic modules is one of the most serious problems in the multimedia VLSI systems on a chip. A logic-in-memory structure, in which logic-circuit elements are distributed over a memory-cell array, is a key technology to solve the above problem. A content-addressable memory (CAM) is one of the typical logic-in-memory VLSIs. However, CAMs have been more complex to build and had lower storage density than a normal memory such as RAMs because of the overhead involved in the storage and logic elements.
In this project, a high-performance multiple-valued CAM based on floating-gate-MOS pass-transistor logic is proposed to perform highly parallel magnitude comparisons in a limited chip area. Multiple-valued stored data in the proposed CAM correspond to the threshold voltage of a floating-gate MOS transistor, so that the CAM cell circuit can be designed by using only a single MOS transistor. Moreover, a logic-in-memory VLSI architecture based on such a multiple-valued floating-gate-MOS pass-transistor network is also proposed to realize parallel arithmetic and logic circuits with multiple-valued inputs and binary outputs. The main results of this project are listed below :
(1) Highly Parallel Magnitude-Comparison Hardware Algorithm for CAMs,
(2) Logic-in-Memory VLSI Architecture Using Floating-Gate MOS-Based Multiple-Valued Pass-Transistor Network,
(3) Functional Pass Gate Based on Ferroelectric Devices and Their Application,
(4) Current/Voltage-Hybrid-Mode Multiple-Valued Integrated Circuits.
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