Development of Implantable FES Ssystem using Custom Integrated Circuit
| Project/Area Number |
09558113
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
Biomedical engineering/Biological material science
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| Research Institution | Saitama University |
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Principal Investigator |
TAKAHASHI Khorou Saitama Univ.Faculty of Eng.Professor Univ., Associate Professor, 工学部, 教授 (10124596)
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| Co-Investigator(Kenkyū-buntansha) |
ISHIKAWA Seiichi Nihon Denki Medical Div.Section Chief, 医療機器事業部, 課長
HANDA Yasunobu Tohoku univ.School of Med.Professor, 医学部, 教授 (00111790)
HOSHIMIYA Nozomu Tohoku Univ.Faculty of Eng.Professor, 工学部, 教授 (50005394)
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| Project Period (FY) |
1997 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 1998: ¥1,700,000 (Direct Cost: ¥1,700,000)
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| Keywords | Functional Electrical Stimulation / Custom Integrated Circuit / Restoration of Motor Function / Implantable System / FES / External Power Supply / FPGA |
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| Research Abstract |
An implantable stimulation unit for multichannel functional electrical stimulation (FES) system applied to the restoration of motor functions has been developed. The stimulation unit implanted in the body is externally controlled and powered by an encoded carrier radio frequency of 1.23 MHz and a continuous frequency of 123 kHz, respectively. Up to 16 independently controlled stimulus output channels are provided, with output channel selection and stimulus pulse amplitude controlled externally by the information transmitted in a packet style. The information to check operating states of the implanted unit is also returned. This bi-directional communication system can increases reliability and safety of the implantable FES system. Miniaturization of the implanted unit has been realized by using MCM (Multi-Chip-Module) for analog circuit and the custom integrated circuit (IC) for digital circuit, respectively. The custom IC has been constructed by standard cell method, and 1.2 mum CMOS technology using 2 metal layers. The circuit was designed with the logic theory CAD tool by Cadence, the simulator by VerilogHDL, and the auto layout tool by CellEnsemble. The fabricated IC was constituted with the sells of 452 and the gates of 1347.
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Report
(3 results)
Research Products
(8 results)
