| Project/Area Number |
09559014
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
広領域
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| Research Institution | Kumamoto University |
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Principal Investigator |
SUEYOSHI Toshinori Kumamoto University, Faculty of Engineering, Professor, 工学部, 教授 (00117136)
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| Co-Investigator(Kenkyū-buntansha) |
SHIROUZU Hiroshi Kyushu Matsushita Electric Co., LTD., Researcher, 技術本部テレコム研究所, 研究員
SHIBAMURA Hidetomo Kumamoto University, Faculty of Engineering, Research Associate, 工学部, 助手 (10264136)
SASAKI Mamoru Kumamoto University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (70235274)
KUGA Morihiro Kumamoto University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (80243989)
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| Project Period (FY) |
1997 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥13,000,000 (Direct Cost: ¥13,000,000)
Fiscal Year 1998: ¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 1997: ¥9,400,000 (Direct Cost: ¥9,400,000)
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| Keywords | Papid Prototyping / EPGA / Logic Partitioning / Hardware Description Language / Large Scale Logic Circuit / System LSI / ラピッドプロトタイピング |
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| Research Abstract |
As mentioned in the research plan, we study Rapid Prototyping Technology for Large Scale Logic Circuits. The followings are major results of the research.
1. We developed interactive logic partitioning method which divides gate level netlist into FPGAs utilizing knowledge of designer. This method enables effective logic partitioning independent of design entries such as schematic capture and hardware description language. Utilization ratio and operation speed of FPGA are improved.
2. In addition to method I., two automatic logic partitioning methods were introduced into rapid prototyping environment, which divide logic circuits from gate level netlist and hardware description language. Combining three partitioning methods provided more efficient prototyping environment.
3. We applied the rapid prototyping environment to VLSI system design education. Adopting Graphical HDL entry tool, design specifications of developing system were immediately utilized design entry. It provided not only effective design methods but also design tool for novice designers.
4. We applied the rapid prototyping environment to image processing LSI design for multimedia equipment. This results show that it provided easily to investigation a suitable architecture for operation speed and circuit size using LPGA.
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