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Implementation and Analysis of Pulse Propagating Networks

Research Project

Project/Area Number 09650081
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Engineering fundamentals
Research InstitutionTokyo Denki University

Principal Investigator

HORIO Yoshihiko  Tokyo Denki University Faculty of Engineering Associate Professor, 工学部, 助教授 (60199544)

Co-Investigator(Kenkyū-buntansha) KANOU Nobuo  Tokyo Denki University Faculty of Engineering Assitant Professor, 工学部, 助手 (30287445)
Project Period (FY) 1997 – 1998
Project Status Completed (Fiscal Year 1998)
Budget Amount *help
¥3,300,000 (Direct Cost: ¥3,300,000)
Fiscal Year 1998: ¥2,300,000 (Direct Cost: ¥2,300,000)
Fiscal Year 1997: ¥1,000,000 (Direct Cost: ¥1,000,000)
KeywordsBrain Modeling / Neural Networks / Real-Number Processing / Analog VLSI / Nonlinear Systems / Dynamical Systems / Neuron Model / Dynamical Cell Assembly / 時空間情報処理 / アナログ情報処理
Research Abstract

It is suggested, from the recent physiological and mathematical studies, that the sophisticated information processing in the brain, in particular in the cortex, is achieved by the neuron that sensitively responses to the fine time structure of asynchronously incoming excitatoly action potentials. The neuron functions as a coincident detector among spatio-temporal input pule trains. Continuous variables and time are important in the spatio-temporal network with coincident detector neurons, because real-number processing is possible with them. The real-number processing is very powerful but cannot be realized by the ordinary digital computer.
In this research, the spatio-temporal processing network is implemented using analog integrated circuit technology where continuous time and variables such as voltage and current are available. First of all, an asynchronous pulse neuron model that is the core element of the asynchronous pulse propagating network is proposed. The response characteristics of the single neuron and neural network composed of numbers of neurons are investigated. As the results, chaotic responses are observed from single neuron, furthermore, dynamical assembly is organized in the network. The dynamical assembly is one candidate of the information coding in the spatio-temporal processing. Secondly, analog circuits for the model neuron, the synapse and the axon are proposed. The delay time of the propagating pulses in the axon circuits can be controlled continuously. Moreover, weight of the synaptic circuit can be altered digitally. Finally, the proposed circuits are fabricated using 1.2 mum CMOS semiconductor technology. Characteristics of the circuits are measured. As a consequence, chaotic responses are confirmed from the chip. Furthermore, pulse delay in the axon circuit is also observed. The possibility of the real-number processing using asynchronous pulse propagating network is shown through the IC implementation

Report

(3 results)
  • 1998 Annual Research Report   Final Research Report Summary
  • 1997 Annual Research Report
  • Research Products

    (45 results)

All Other

All Publications (45 results)

  • [Publications] M.Hanagata, Y.Horio and K.Aihara: "Asynchronous pulse neural network model for VLSI implementation" Trans. on Fundamentals, IEICE. E81A, 9. 1853-1859 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] Y.Horio: "Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions" Report of the Research Institute for Technology, Tokyo Denki University. 9, 1. 1-2.1-1-2.11 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 当麻喜弘, 三谷政昭, 斉藤剛, 稲葉博, 堀尾喜彦, 簑原隆: "ニューロ素子の高機能化とニューラルネットワークの高次処理に関する研究" 東京電機大学総合研究所年報. 17. 147-156 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 花形満, 堀尾喜彦, 合原一幸: "VLSI化を目的とした非同期パルスニューラルネットワークモデル" 電子情報通信学会技術報告. NLP97, 530. 29-35 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] Y.Horio, K.Yasuda, M.Hanagata and K.Aihara: "An asynchronous pulse neural network model and its analog IC implementation" Proc.Int.Conf.on Electronics, Circuits and Systems. 3. 301-304 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] Y.Horio, M.Hanagata and K.Yasuda: "An asynchronous pulse neural network model and its analog circuit implementation" Proc.Int.Symp.on Artificial Life and Robotics. 2. 336-341 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 渡来賢一, 堀尾喜彦: "連続時間遅延を持つ軸索回路の一構成法" 電子情報通信学会全国大会論文集. 1. 22 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 安田和秀, 花形満, 堀尾喜彦: "非同期パルスニューロンモデルの集積回路化" 電子情報通信学会全国大会論文集. 1. 65 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] K.Yasuda, M.Hanagata R.Kasahara and Y.Horio: "Analog circuit implementation of asynchronous pulse neural network model" Proc.Int.Symp.on Nonlinear Theory and Its Applications. 2. 853-856 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] M.Hanagata and Y.Horio: "A modified asynchronous pulse neural network model for VLSI implementation" Proc.Int.Symp.on Nonlinear Theory and Its Applications. 2. 849-852 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] M.Hanagata and Y.Horio: "An asynchronous pulse neural network model with finite pulse width for VLSI implementation" Proc.Int.Conf.on Neural Information Processing and Intelligent Information Systems. 1. 26-29 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] M.Hanagata and Y.Horio: "A modified asynchronous chaos neural network model for VLSI implementation" Proc.Int.Symp.on Circuits and Systems. 1. 657-661 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] 堀尾 喜彦: "カオスニューロコンピュータ" Computer Today. 14, 5. 14-21 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] M.Hanagata, Y.Horio and K.Aihara: "Asynchronous pulse neural network model for VLSI implementation" Trans.on Fundamentals, IEICE. E81A-9. 1853-1859 (1988)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] Y.Horio: "Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions" Report of the Research Institute for Technology, Tokyo Denki University. 9-1. 1-2.1-1-2.11 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] Y.Tohma, M.Mitani, T.Saito, H.Inaba, Y.Horio and T.Minohara: "Developing neurons with a higher functioning capability and utilizing advanced methodologies to solve problems by neural networks" Annual Report of the Research Institute for Technology, TDU. 17. 147-156 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] M.Hangata, Y.Horio and K.Aihara: "Asynchronous pulse neural network model for VLSI implementation" Tech.Rep.IEICE. NLP97-530. 29-35 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] Y.Horio, K.Yasuda, M.Hanagata and K.Aihara: "An asynchronous pulse neural network model and its analog IC implementation" Proc.Int.Conf.on Electronics, Circuits and Systems. 3. 301-304 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] Y.Horio, M.Hanagata and K.Yasuda: "An asynchronous pulse neural network model and its analog circuit implementation" Proc.Int.Symp.on Artificial Life and Robotics. 2. 336-341 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] K.Watarai, Y.Horio: "Axon circuit with continuously controlled pulse delay" Proc.Annual Meeting of IEICE. 1. 22 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] K.Yasuda, M.Hanagata and Y.Horio: "IC implementation of asynchronous pulse neuron mdel" Proc.Annual Meeting of IEICE. 1. 65 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] K.Yasuda, M.Hanagata R.Kasahara and Y.Horio: "Analog circuit implementation of asynchronous pulse neural network model" Proc.Int.Symp.on Nonlinear Theory and Its Applications. 2. 853-856 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] M.Hanagata and Y.Horio: "A modified asynchronous pulse neural network model for VLSI implementation" Proc.Int.Symp.on Nonlinear Theory and Its Applications. 2. 849-852 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] M.Hanagata and Y.Horio: "An asynchronous pulse neural network model with finite pulse width for VLSI implementation" Proc.Int.Conf.on Neural Information Processing and Intelligent Information Systems. 1. 26-29 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] M.Hanagata and Y.Horio: "A modified asynchronous chaaos neural network model for VLSI implementation" Proc.Int.Sump.on Circuits and Systems. 1. 657-661 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] Y.Horio: "Chaotic neuro-computer" Computer Today. 14-5. 14-21 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1998 Final Research Report Summary
  • [Publications] M.Hanagata,Y.Horio and K.Aihara: "Asynchronous pulse neural network model for VLSI implementation" Trans.on Fundamentals,IEICE. E81A,9. 1853-1859 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] Y.Horio: "Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions" Report of the Research Institute for technology,Tokyo Denki University. 9,1. 1-2.1-1-2.11 (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] 当麻喜弘,三谷政昭,斉藤剛,稲葉博,堀尾喜彦,簑原隆: "ニューロ素子の高機能化とニューラルネットワークの高次処理に関する研究" 東京電機大学総合研究所年報. 17. 147-156 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 花形満,堀尾喜彦,合原一幸: "VLSI化を目的とした非同期パルスニューラルネットワークモデル" 電子情報通信学会技術報告. NLP97,530. 29-35 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] Y.Horio,K.Yasuda,M.hanagata and K.Aihara: "An asynchronous pulse neural network model and its analog IC implementation" Proc.Int.Conf.on Electronics,Circuits and Systems. 3. 301-304 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] Y.Horio,M.Hanagata and K.Yasuda: "An asynchronous pulse neural network model and its analog circuit implementation" Proc.Int.Symp.on Artificial Life and Robotics. 2. 336-341 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 渡来賢一,堀尾喜彦: "連続時間遅延を持つ軸索回路の一構成法" 電子情報通信学会全国大会論文集. 1. 22 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 安田和秀,花形満,堀尾喜彦: "非同期パルスニューロンモデルの集積回路化" 電子情報通信学会全国大会論文集. 1. 65 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] K.Yasuda,M.Hanagata R.Kasahara and Y.Horio: "Analog circuit implementation of asynchronous pulse neural network model" Proc.Int.Symp.on Nonlinear Theory and Its Applications. 2. 853-856 (1997)

    • Related Report
      1998 Annual Research Report
  • [Publications] M.Hanagata and Y.Horio: "A modified asynchronous pulse neural network model for VLSI implementation" Proc.Int.Symp.on Nonlinear Theory and Its Applications. 2. 849-852 (1997)

    • Related Report
      1998 Annual Research Report
  • [Publications] M.Hanagata and Y.Horio: "An asynchronous pulse neural network model with finite pulse width for VLSI implementation" Proc.Int.Conf.on Neural Information Processing and Intelligent Information Systems. 1. 26-29 (1997)

    • Related Report
      1998 Annual Research Report
  • [Publications] M.Hanagata and Y.Horio: "A modified asynchronous chaos neural network model for VLSI implementation" Proc.Int.Symp.on Circuits and Systems. 1. 657-661 (1997)

    • Related Report
      1998 Annual Research Report
  • [Publications] 堀尾 喜彦: "カオスニューロコンピュータ" Computer Today. 14,5. 14-21 (1997)

    • Related Report
      1998 Annual Research Report
  • [Publications] M.Hanagata and Y.Horio: "A modified asynchronous chaotic neural network model for VLSI implementation" Proc.of Int.Symp.on Circuits and Systems. 1. 657-661 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] M.Hanagata and Y.Horio: "An asynchronous pulse neural network model with finite pulse width for VLSI implementation" Proc.of Int.Conf.on Neural Inf.Proc.and Intelligent Inf.Syst.1. 26-29 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] M.Hanagata and Y.Horio: "A modified asynchronous pulse neural network model for VLSI implementation" Proc.of Int.Symp.on Nonlinear Theory and Its Applications. 2. 849-852 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] K.Yasuda, M.Hanagata, R.Kasahara and Y.Horio: "Analog circuit implementation of asynchronous pulse neural network model" Proc.of Int.Symp.on Nonlinear Theory and Its Applications. 2. 853-856 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] Y.Horio, M.Hanagata and H.Yasuda: "An asynchronous pulse neural network model and its analog circuit implementation" Proc.of Int.Symp.on Artificial Life and Robotics. 1. 336-341 (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] 花形満, 堀尾喜彦, 合原一幸: "VLSI化を目的とした非同期パルスニューラルネットワークモデル" 電子情報通信学会技術報告. 97,530. 29-35 (1998)

    • Related Report
      1997 Annual Research Report

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Published: 1997-04-01   Modified: 2016-04-21  

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