| Project/Area Number |
09650383
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
ONODERA Hidetoshi Kyoto University, Dept.of Communications and Computer Engineering, Associate Professor, 情報学研究科, 助教授 (80160927)
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| Co-Investigator(Kenkyū-buntansha) |
KOBAYASHI Kazutoshi Kyoto University, Dept.of Communications and Computer Engineering, Research Asso, 情報学研究科, 助手 (70252476)
TAMARU Keikichi Kyoto University, Dept.of Communications and Computer Engineering, Professor, 情報学研究科, 教授 (10127102)
VASILY Moshn 京都大学, 工学研究科, 講師 (40243050)
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| Project Period (FY) |
1997 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥3,800,000 (Direct Cost: ¥3,800,000)
Fiscal Year 1998: ¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 1997: ¥2,100,000 (Direct Cost: ¥2,100,000)
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| Keywords | optimization of detailed design / Low power design / High speed design / Cell-base design / Library generation / Standard cell library / Gate sizing / Input reordering / 詳細設計 / 低消費電力化 / クロストーク / 遅延最小化 / ディープサブミクロンプロセス / ASIC / システムLSI / 物理設計 / 遅延最適化 / 消費電力モデル / 遅延時間モデル / CMOS理論ゲート / 最適化設計 |
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| Research Abstract |
We have studied design optimization methods for UDSM integrated circuits. In particular, we have developed a gate-level optimization method combined with layout design(we call this "detailed design") and its related techniques.
In the detailed design, accurate delay and power estimation are necessary. We have developed an quasi-analytical method for delay and power estimation of CMOS gates driving a CRC pi load. The error of the estimated delay is around 3% in average while the calculation speed is 1000 times faster than circuit simulation.
The target of the detailed design optimization is a cell-base designed ASIC.In this case, the performance of the cell library directly affects the performance of the designed ASIC.We have developed a generation system of a standard cell library with optimized performance for a target design.
As for the methods for detailed design optimization, we have worked on input reordering and gate sizing. Power dissipation, as well as delay, is optimized by these methods. We have focused on the power dissipated by glitches. Considering glitch reduction in the optimization process, we have succeeded to reduce power dissipation further from the minimum sized circuit that has the lowest capacitive load.
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