A Study on fully inverted SIMOX MOSFETs
| Project/Area Number |
09650389
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Toyo University |
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Principal Investigator |
SUGANO Takuo Toyo Univ. Faculty of Eng. Prof., 工学部, 教授 (50010707)
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| Co-Investigator(Kenkyū-buntansha) |
HANAJIRI Tatsuro Toyo Univ.Dept.of Electroniceng Assistant Prof., 工学部, 助教授 (30266994)
TOYABE Toru Toyo Univ.Dept.of Computer science Prof., 工学部, 教授 (20266993)
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| Project Period (FY) |
1997 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,900,000)
Fiscal Year 1998: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1997: ¥2,800,000 (Direct Cost: ¥2,800,000)
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| Keywords | SOI MOSFET / fully inverted / threshold voltage / top Si layer / low power supply / high packing density / short signal delay / 2次元電子状態 / 臨界膜厚 / サブヌレッショルド特性 / 伝達コンダクタンス特性 / シリコン超薄膜 / SIMOX基板 / 完全反転型SOI MOSFET / 低闘値電圧 / 低サブスレッショルド係数 / 高相互コンダクタンス / 完全反転臨界膜厚 / 電子ビーム蒸着装置 / トップシリコン層 |
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| Research Abstract |
Electrical characteristics of SOI MOSFETs was investigated by the device sirnulator CADDETH and it is found that threshold voltage is reduced to aroud 1(v)and short channel effect was suppressed by Fully Inverted (F1)SOI MOSFETs, which were proposed by the authors.
The FI(fully inverted)SOI MOSFET is a novel type of SOI MOSFETs where the whole region of the top silicon layer is inverted completely. In FI SOI MOSFETs, the depleted region is eliminated by thinning the top silicon layer, and the gate electric field induces charge in the channel more effectively than in the fully depleted(FD)SOI MOSFET<s. In consequence, FI SOI MOSFETs are expected to have advantages that the threshold voltage(VィイD2thィエD2)can be lowered maintaining dopant density high and also the short channel effect can be suppressed substantially. In FI SOI MOSFETs, the depleted region is eliminated by thinning the top silicon layer, and the gate electric field induces charge in the channel more effectively than in the fully depleted(FD)SOI MOSFETs. In consequence, it is found that in FI SOI MOSFETs, the threshold voltage(VィイD2thィエD2)can be lowered keepnig dopant density high and also the roll-off of VィイD2thィエD2 can be suppressed substantially. The behavior of VィイD2thィエD2 in SOI MOSFETs is shown in the figure. When the thickness of top Si layer(tィイD2SiィエD2)is less than 10(nm), and MOSFET is in FI mode, the dependence of VィイD2thィエD2 on tィイD2SiィエD2 is suppressed remarkably.
FI SOI MOSFETs can realize high packing density, short signal propagation delay, together with a low voltage power supply less than 1V, and are one of the most feasible devices for low power VLSI.
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Report
(3 results)
Research Products
(11 results)
