| Co-Investigator(Kenkyū-buntansha) |
HIRAKAWA Takuya Kyushu Institute of Technology, Faculty of Computer Science and Systems Engineer, 情報工学部, 助手 (30304869)
TSUJINO Taro Osaka University, Computer Center, Research Associate (1977 only), 大型計算機センター, 助手 (00227406)
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| Budget Amount *help |
¥2,600,000 (Direct Cost: ¥2,600,000)
Fiscal Year 1998: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 1997: ¥1,600,000 (Direct Cost: ¥1,600,000)
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| Research Abstract |
Since software controllers are slow in high-order cases, such as in the H_* control, hardware is sometimes incorporated. Large circuit size, especially caused by multipliers, poses problems then. The project goal is to realize controllers with 100 times faster speed, by both reducing circuit and shortening the time of development.
The actual mechanism is based on the fact that multiplication in controllers are usually with constant coefficients : multiplication k^* x is not considered to have two inputs, but is a function f(x) with x input only ; then, the circuit to derive f(x) from x is realized by logic synthesis.
Linear operation of k1^* x1 + k2^* x2 + ... kn^* xn is implemented by combining synthesized constant coefficienters and an adder. Time of logic synthesis is further reduced by halving long input words and adding the two outputs. As a result, time of logic synthesis is reduced down to at least 1/5, circuit size to at least 1/4. In addition, a feature that their increments for order increment is linear is verified.
Because f(x) depends on design, implementation is accomplished with programmable ASIC'S (FPGA's). Based on this feature, a prototype development system is constructed on a notebook PC to be used on site, and a controller with sample frequency of 300kHz is successfully implemented. This speed is about 30 times faster than software controllers with a DSP's. Though the controller order is 2, sample rate will be no slower than 200kHz even if the order is 20.
As described, the project goal, to develop high-order hardware controllers efficiently in both size and time, is considered to be attained. Some design method with constrained gain coefficients, to realize the desired specification while further reducing circuit size, will be investigated in the future.
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