| Project/Area Number |
09680334
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
計算機科学
|
|---|
| Research Institution | KYOTO UNIVERSITY |
|---|
Principal Investigator |
MORI Shin-ichiro Kyoto University, Graduate School of Informatics, Associate, Professor, 情報学研究科, 助教授 (20243058)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
GOSHIMA Masahiro Kyoto University, Graduate School of Informatics, Research, Associate, 情報学研究科, 助手 (90283639)
|
|---|
| Project Period (FY) |
1997 – 1999
|
| Project Status |
Completed (Fiscal Year 1999)
|
| Budget Amount *help |
¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 1999: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1998: ¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 1997: ¥1,600,000 (Direct Cost: ¥1,600,000)
|
|---|
| Keywords | Distributed Shared Memory / Cache / Coherency Controll / Parallel Processing / Network Computer / NCC-NUMA / CC-NUMA / Self Cleanup Cache / NCC-MUMA / CC-MUMA / ネットワーク共有メモリ |
|---|
| Research Abstract |
In order to investigate the essential ability of the Non-Cache-Coherent NUMA system configured with write-back cache, we assumed an NCC-NUMA Architecture configured with Self-Cleanup Cache, which has an ability to enforce the write back of unused dirty line without invalidating the line, and evaluated its performance by simulation works.
The result of the simulation showed that 1) NCC-NUMA System can achieve comparable performance to CC-NUMA system if some moderate optimizations are forced to the application program, 2) NCC-NUMA System outperforms CC-NUMA System if the network latency arrives to the order of 100 processor cycle, and 3) the performance gain of NCC-NUMA System to CC-NUMA System increases with the increase of the network latency for the well optimized application programs.
We also found that, however, for some programs which were optimized to increase the memory access locality with the techniques like privatization or blocking, the self-invalidation and the self-cleanup of shared data placed in the local memory have a possibility of affecting the performance.
To deal with this problem, we have proposed the Self-Cleanup Cache with 2bit Directory Scheme. By configuring a 2bit directory with each local memory and maintain the local caching status, intra-node cache coherence in this system is maintained like the other directory based system, so that unnecessary invalidations and self-cleanups of locally cached data disappear. After further study of this scheme, we found that the Self-Cleanup Cache with 2bit Directory Scheme is well applicable to the SMP Cluster system, which adopts the one-chip multiprocessor in particular.
|
