| Project/Area Number |
09680338
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Osaka University |
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Principal Investigator |
KITAMICHI Junji Graduate School of Engineering Science, Osaka University, Tutor, 情報処理教育センター, 講師 (20234271)
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| Co-Investigator(Kenkyū-buntansha) |
HIGASHINO Teruo Graduate School of Engineering Science, Osaka University, Professor, 大学院・基礎工学研究科, 教授 (80173144)
FUNABIKI Nobuo Graduate School of Engineering Science, Osaka University, Assistant Professor, 大学院・基礎工学研究科, 助教授 (70263225)
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| Project Period (FY) |
1997 – 1999
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| Project Status |
Completed (Fiscal Year 1999)
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| Budget Amount *help |
¥3,200,000 (Direct Cost: ¥3,200,000)
Fiscal Year 1999: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 1998: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1997: ¥1,700,000 (Direct Cost: ¥1,700,000)
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| Keywords | Dynamically Reconfigurable Logic / Multi Context / FPGA / Simulated Annealing / Greedy / Partition / CAD / Neural Network |
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| Research Abstract |
In this study, We propose an implementation method of a Multi-Context Dynamically Reconfigurable FPGA and a CAD algorithm for optimal use of it. Multi-Context Dynamically Reconfigurable FPGA is a VLSI which can be programmed during system operation with better reconfiguration time-efficiency than conventional Reconfigurable FPGA. We evaluated the hardware cost to add the Multi-Context Dynamically Reconfigurable FPGA by the result of synthesis of the hardware description of the Multi-Context Dynamically Reconfigurable FPGA. And We also evaluated the improvement of CLB (Configurable Logic Block) or bus usage by the implementation of the Neural Network Algorithm compared with conventional Reconfigurable FPGA. The CAD algorithm for Multi-Context FPGA minimizes reconfiguration time overhead proportional to the amount of the reconfiguration data. It inputs a finite state machine and outputs subsets of states called pages which is a reconfiguration unit of Multi-Context FPGA. The performance of the proposed algorithm is demonstrated experimentally.
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