| Project/Area Number |
09680344
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Kumamoto University |
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Principal Investigator |
SUEYOSHI Toshinori Kumamoto Univesity, Faculty of Engineering, Professor, 工学部, 教授 (00117136)
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| Co-Investigator(Kenkyū-buntansha) |
NAKASHIMA Takuo Kumamoto University, Faculty of Engineering, Research Associate, 工学部, 助手 (90237256)
SHIBAMURA Hidetomo Kumamoto University, Faculty of Engineering, Research Associate, 工学部, 助手 (10264136)
KUGA Morihiro Kumamoto University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (80243989)
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| Project Period (FY) |
1997 – 1998
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| Project Status |
Completed (Fiscal Year 1998)
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| Budget Amount *help |
¥3,200,000 (Direct Cost: ¥3,200,000)
Fiscal Year 1998: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1997: ¥2,100,000 (Direct Cost: ¥2,100,000)
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| Keywords | Reconfigurable Processor / Reconfigurable Computing / Reconfigurable Structure / Reconfigurable Logic / FPGA / Multi-thread / Data Driven / Control Driven / リコンフィギャラブル・プロセッサ / 計算機アーキテクチャ / システム・オン・シリコン |
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| Research Abstract |
As mentioned in the research plan, we study Reconfigurable Processor using Reconfigurable LSI.The followings are major results of the research.
1. A system prototype of on-chip multiprocessor using system-on-silicon technology was considered as a part of basic research for reconfigurable processor. The system employed the reconfigurability that is a feature of reconfigurable processor and the speed up by hardware implementation. The reconfiguration feature was adapted to hardware with thread control mechanism and its architecture was described. A reconfigurable logic with the dynamic reconfiguration feature which can ignore its overhead of reconfiguration enables that the processor execute both the processor synchronization and the thread scheduling in parallel, and high performance was achieved.
2. Java was selected as a programming language to write applications and it stands for a part of program development environment for reconfigurable processor. Java is suited for writing parallel applications because it supports concurrent programming in its language specification. A prototype program that translates from Java to hardware description language was developed and this translator was realized with consideration for not only simulation but also implementation into FPGAs.
3. We applied the reconfigurable processor to three applications ; Fast Fourier Transform (FFT), N Queens problem, and LAN simulator. Evaluation results showed advantages about 180 times speed up comparison with conventional workstation in applications including highly parallelism. Also, 10 times speed up was recognized in applications restricted parallelism with hardware resource limitation.
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