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Neural LSI's Possessing Autonomous Defect Self-repairing Capability

Research Project

Project/Area Number 10450131
Research Category

Grant-in-Aid for Scientific Research (B).

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionUniversity of Tsukuba

Principal Investigator

YASUNAGA Moritoshi  Institute of Information Sci. & Electro. University of Tsukuba Associate Processor, 電子・情報工学系, 助教授 (80272178)

Project Period (FY) 1998 – 2000
Project Status Completed (Fiscal Year 2000)
Budget Amount *help
¥4,500,000 (Direct Cost: ¥4,500,000)
Fiscal Year 2000: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 1999: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 1998: ¥1,600,000 (Direct Cost: ¥1,600,000)
KeywordsNeural Networks / Integrated Circuit / Genetic Algorithms / Fault Tolerance / Biological Information / Fault / Defect / Pattern Recognition / 自律システム / 自己組織化
Research Abstract

We have chosen the self-organizing map (SOM) as the target network in the neural networks, and evaluated its autonomous fault repairing capability quantitatively. Especially, in the project, we have proposed a defect model in which the defective neurons output arbitrary stuck values. From the analysis of the model, the following facts are shown (proved).
1) The SOM can repair the defective neurons autonomously, if the defective neurons'outputs are larger than the critical stuck output, which is derived from the proposed defect model.
2) The new criteria "critical stuck output" can be used widely even in the real applications such as image compression and face image recognition.
Furthermore, in the project, we have also evaluated fault tolerance of the evolutionary algorithm (genetic algorithms, genetic program etc.) because the high fault tolerance can be also expected not only in the neural networks but also other algorithms based on the biological information processing. In order to evaluate the fault tolerance, we have carried out fault injection experiments using simulation programs and the prototype machine constructed based on reconfigurable LSI (FPGA). From the experimental results, it has been shown that the hardware based on the evolutionary algorithms also has high fault tolerance and graceful degradation against defective circuits
From wll those experimental results we have show that neural network LSIs and evolutionary algorithms-based LSIs has high fault tolerance and they can repair the defective circuits autonomously.

Report

(4 results)
  • 2000 Annual Research Report   Final Research Report Summary
  • 1999 Annual Research Report
  • 1998 Annual Research Report
  • Research Products

    (35 results)

All Other

All Publications (35 results)

  • [Publications] 安永守利,八谷一平: "自己組織化マップハードウェアのフォールトトレランス評価"電子情報通信学会論文誌. Vol.J82-D-1,No.2. 410-424 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] 安永守利,高橋雅聡,吉原郁夫: "進化的手法に基づく再構成可能な推論ハードウェア"情報処理学会論文誌. Vol.40,No.7. 3031-3042 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Yasunaga,T.Nakamura,and I.Yoshihara: "Sonar Spectrum Recognition Chip Designed by Evolutionary Algorithm"Proc. The IEEE and INNS Intl. Joint Conf. on Neural Networks. (CD-ROM). (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Yasunaga,T.Nakamura,and I.Yoshihara: "Biometrics Identification Chip and Its Design Using Evolutionary Algorithm"International Symposium on Nonlinear Theory and its Applications. 235-238 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga,Jung H.Kim,and Ikuo Yoshihara: "The Application of Genetic Algorithms to the Design of Reconfigurable Reasoning VLSI Chips"ACM/SIGDA Proc.Int.Sympo. on Field Programmable Gate Arrays. 116-125 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] 都竹高広,高島浩二,安永守利: "進化ハードウェアの耐故障性能の検討"電子情報通信学会総合大会講演集. 170 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga et.al.: "Genetic Algorithm-based Design Methodology for Pattern Recognition Hardware"Proc.Int.Conf. on Evolvable Systems (Springer LNCS No.1801). 264-273 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga et.al.: "Kernel-based Pattern Recognition Hardware : Its Design Methodology Using Evolved Truth Tables"Proc.The 2nd NASA/DoD Workshop on Evolvable Hardware. 253-262 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga et.al.: "GA-based Kernel Optimization for Pattern Recognition : Theory for EHW Application"Proc.IEEE Congress on Evolutionary Computation. 545-552 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga et.al.: "A Bus-based Neuro-computer for High Speed SOM Calculation and Its Fault Tolerance against Defective Circuits"Proc.the 6th Int.Conf.Soft Computing IIZUKA2000. 264-271 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga et.al.: "A High Speed and High Fault Tolerant Reconfigurable Reasoning System : Toward a Wafer Scale Reconfigurable Reasoning LSI"Proc.IEEE Int.Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2000). 69-77 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Yasunaga and I.Hachiya: "Fault-Tolerance Evaluation of Self-Organizing Map Hardware"Journal of IEICE Japan. Vol.J82-D-1, No.2. 410-424 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Yasunaga, M.Takahashi, and I.Yoshihara: "Reconfigurable Reasoning Hardware by Using Evolutionary Algorithm"Journal of IPSJ. Vol.40, No.7. 3031-3042 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga, Taro Nakamura, and Ikuo Yoshihara: "Sonar Spectrum Recognition Chip Designed by Evolutionary Algorithm"Proc. The IEEE and INNS Intl. Joint Conf. on Neural Networks, CD-ROM July. (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga, Taro Nakamura, and Ikuo Yoshihara: "Biometrics Identification Chip and Its Design Using Evolutionary Algorithm"Proc. International Symposium on Nonlinear Theory and its Applications, Hawaii. 235-238 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga, Jung H.Kim, and Ikuo Yoshihara: "The Application of Genetic Algorithms to the Design of Reconfigurable Reasoning VLSI Chips, ""Proc. ACM/SIGDA Proc. Int.Sympo. on Field Programmable Gate Arrays, Monterey. 116-125 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, and Jung H.Kim: "Genetic Algorithm-based Design Methodology for Pattern Recognition Hardware"Proc.Int.Conf. on Evolvable Systems (Springer LNCS No.1801) Edinburgh. 264-273 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga, Taro Nakamura, Jung H.Kim, and Ikuo Yoshihara: "Kernel-based Pattern Recognition hardware : Its Design Methodology Using Evolved Truth Tables"Proc. The 2nd NASA/DoD Workshop on Evolvable Hardware. 253-262 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, and Jung H.Kim: "GA-based Kernel Optimization for Pattern Recognition : Theory for EHW Application"Proc.IEEE Congress on Evolutionary Computation. 545-552 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga, Keiji Moki, Jung H.Kim, and Ikuo Yoshihara: "A Bus-based Neuro-computer for High Speed SOM Calculation and Its Fault Tolerance against Defective Circuits"Proc. the 6th Int.Conf.Soft Computing IIZUKA2000, INVITED TALK. 264-271 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga, Ikuo Yoshihara, and Jung H.Kim: "A High Speed and High Fault Tolerant Reconfigurable Reasoning System : Toward a Wafer Scale Reconfigurable Reasoning LSI"Proc.IEEE Int.Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2000). 69-77 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] T.Tsuzuku, K.Takashima, and M.Yasunaga: "Study on the Fault Tolerance of Evolvable Hardware"Proc.IEICE Sougou-Taikai. D-10-23. 170 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Moritoshi Yasunaga et.al.: "Genetic Algorithm-based Design Methodology for Pattern Recognition Hardware"Proc.Int.Conf.on Evolvable Systems (Springer LNCS No.1801). 264-273 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] Moritoshi Yasunaga et.al.: "Kernel-based Pattern Recognition Hardware : Its Design Methodology Using Evolved Truth Tables"Proc.The 2nd NASA/DoD Workshop on Evolvable Hardware. 253-262 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] Moritoshi Yasunaga et.al.: "GA-based Kernel Optimization for Pattern Recognition : Theory for EHW Application"Proc.IEEE Congress on Evolutionary Computation. 545-552 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] Moritoshi Yasunaga et.al.: "A Bus-based Neuro-computer for High Speed SOM Calculation and Its Fault Tolerance against Defective Circuits"Proc.the 6th Int.Conf.Soft Computing IIZUKA2000. 264-271 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] Moritoshi Yasunaga et.al.: "A High Speed and High Fault Tolerant Reconfigurable Reasoning System : Toward a Wafer Scale Reconfigurable Reasoning LSI"Proc.IEEE Int.Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2000). 69-77 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 都竹高広,高島浩二,安永守利: "進化ハードウェアの耐故障性能の検討"電子情報通信学会総合大会講演集. (掲載予定). (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 中村太郎,安永守利: "高い耐故障性能を持つパターン認識用集積回路の検討"電子情報通信学会信学技報. FIIS99 NO.55. 1-11 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 安永守利: "進化アルゴリズムによる超高速・耐故障パターン認識チップの開発"計測自動制御学会創発システムシンポジウム予稿集. 1-6 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Moritoshi Yasunaga et.al: "Evolbable Sonar Spectrum Discnmination Chip Designed by Genetic Algorithm"Proc.IEEE Intl.Conf.Systems,Man,and Cybernetics. V585-V590 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Moritoshi Yasunaga et.al: "A Fault-tolerant Evoluable Face Identification Chip"Proc.Intl.Conf.Neural Information Processing. 125-130 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Moritoshi Yasunaga et.al: "The Application of Genetic Algorithm to the Design of Reconfigurable Reason VLSI Chips"Proc.ACM Intl.Symp.Field Programmable Gate Arrays. 116-125 (2000)

    • Related Report
      1999 Annual Research Report
  • [Publications] 安永守利,八谷一平: "自己組織化マップ集積回路の自律的な故障修復"SOM研究会予稿集. 1-6 (2000)

    • Related Report
      1999 Annual Research Report
  • [Publications] 安永守利,八谷一平: "自己組織化マップハードウェアのフォールトトレランス評価" 電子情報通信学会論文誌. Vol.J82DI No.2. 410-424 (1999)

    • Related Report
      1998 Annual Research Report

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Published: 1998-04-01   Modified: 2016-04-21  

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