| Project/Area Number |
10450137
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| Research Category |
Grant-in-Aid for Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Osaka University |
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Principal Investigator |
FUJIOKA Hiromu Osaka University, Graduate School of Engineering, Professor, 大学院・工学研究科, 教授 (40029228)
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| Co-Investigator(Kenkyū-buntansha) |
MIURA Katsuyoshi Osaka University, Graduate School of Engineering, Research Associate, 大学院・工学研究科, 助手 (30263221)
NAKAMAE Koji Osaka University, Graduate School of Engineering, Associate Professor, 大学院・工学研究科, 助教授 (40155809)
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| Project Period (FY) |
1998 – 2000
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| Project Status |
Completed (Fiscal Year 2000)
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| Budget Amount *help |
¥9,500,000 (Direct Cost: ¥9,500,000)
Fiscal Year 2000: ¥2,300,000 (Direct Cost: ¥2,300,000)
Fiscal Year 1999: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 1998: ¥4,800,000 (Direct Cost: ¥4,800,000)
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| Keywords | design for testability / LSI with multi-layer structure / test pad / current testing / current test point / fault localization / EB testability / VLSI / パーティクル |
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| Research Abstract |
The electron beam (EB) test system has been widely used to measure internal signal behavior in LSI.However, with an advance in the LSI manufacturing, there has been a tendency to design an LSI with a multi-layer structure. This multi-layer structure causes the decrease in testability of the EB test system.
In order to alleviate the difficulties in testing LSIs, we develop the test pad introduction tool and propose the current test points that complement the voltage test points.
The former test pad means the electrode on the uppermost layer connected to the electrode on the lower layer to be measured. We designed the test pad cell with area as small as possible to be probed with an EB tester. Then the number and the insertion positions of test pads are determined to narrow down the faulty area size to the specified number of primitive cells. By applying the test pad introduction tool to the self-made 8-bit microprocessor LSI, the improvement in testability of the EB test system and the performance deterioration such as the delay time were examined. Results shows that the faulty area size of about 1300 was improved to 100 by introducing 50 test pads and the performance deterioration could be neglected.
The latter current test point passes an electric current with a prescribed value when the control signal is set at a test mode. By checking whether the total power supply current is equal to the sum of the prescribed current values or not, we know the device under test (DUT) is faulty or not. When the control signal is set at a normal mode, the DUT performs normal operations. We established the design method of current test point cells under various constraints such as process variations.
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