| Project/Area Number |
10450151
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
情報通信工学
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| Research Institution | Osaka University |
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Principal Investigator |
SHIRAKAWA Isao Department of Information Systems Engineering, Osaka University, Professor, 大学院・工学研究科, 教授 (10029100)
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| Co-Investigator(Kenkyū-buntansha) |
FUJITA Gen Center of Advanced Research Projects, Osaka University, Research Assistant, 先導的研究オープンセンター, 助手 (30304025)
ONOYE Takao Department of Communications and Computer Engineering, Kyoto University, Associate Professor, 大学院・情報学研究科, 助教授 (60252590)
ISHIURA Nagisa Department of Information Systems Engineering, Osaka University, Associate Professor, 大学院・工学研究科, 助教授 (60193265)
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| Project Period (FY) |
1998 – 1999
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| Project Status |
Completed (Fiscal Year 1999)
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| Budget Amount *help |
¥6,000,000 (Direct Cost: ¥6,000,000)
Fiscal Year 1999: ¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 1998: ¥3,900,000 (Direct Cost: ¥3,900,000)
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| Keywords | MPEG-4 / VLSI implementation / low power / retargetable compiler / DSP / リターゲッタブルコンパイラ / MPEG4 / コンパイラ |
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| Research Abstract |
In this project, we developed new architectures for MPEG-4 audio and video compression for wireless communication. We also attempted to implement VLSIs based on the architectures. We developed an architecture for H.324 encoder/decode, which is closely related to MPEG-4, based on dedicated hardware components. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The designed audiovisual codec core has been implemented by using 0.35μm CMOS 4LM technology, which contains totally 420k transistors with the dissipation of 224.32mW from single 3.3V supply.
Furthermore, we implementated an MPEG-4 audio decoder, which is dedicated to portable audio appliances. Based on the results of sound quality evaluation, we devise a low-power architecture for each module such as utilization of frame-level pipeline architecture, optimization of functional datapath, etc.
We developed a retargetable compiler which is used for application specific DSPs, such as the G.723.1 speech codec DSP.
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