| Project/Area Number |
10480058
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| Research Category |
Grant-in-Aid for Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
HIBINO Yasushi Japan Advanced Institute of Science and Technology School of Information Science, Professor, 情報科学研究科, 教授 (10251969)
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| Co-Investigator(Kenkyū-buntansha) |
TAN Yasuo Japan Advanced Institute of Science and Technology School of Information Science, Associate Professor, 情報科学センター, 助教授 (90251967)
MIYAZAKI Jun Japan Advanced Institute of Science and Technology School of Information Science, Research Associate (40293394)
YOKOTA Haruo Tokyo Institute of Technology Graduate School of Information Science and Technology, Associate Professor (10242570)
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| Project Period (FY) |
1998 – 2000
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| Project Status |
Completed (Fiscal Year 2000)
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| Budget Amount *help |
¥9,600,000 (Direct Cost: ¥9,600,000)
Fiscal Year 2000: ¥1,200,000 (Direct Cost: ¥1,200,000)
Fiscal Year 1999: ¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 1998: ¥4,700,000 (Direct Cost: ¥4,700,000)
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| Keywords | computer architecture / Pipeline / mutlithread / wave pipeline / MOS device / CMOS / delay / wiring delay / delay balancing / low power comsumption / 遅延均衡 / 低消費電力設計 / パイプラインキャッシュ / メモリシステム |
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| Research Abstract |
As shrinking the dimension of Metal Oxide Semiconductor (MOS) devices according to the scaling down rule, the switching delay time of MOS transistor decreases in proportional to the scaling factor. So, the operating frequency goes up relying upon progress of the fine fabrication process technology.
However, the wiring delay time is invariable for the scaling rule because of a law of electromagnetism. That is, the wiring resistance increases in inverse proportion to scaling factor while the wiring capacitance decreases in proportion to scaling factor. Therefore, when the fabrication process technology becomes extremely fine, it is difficult to increase the operating frequency of the processor chip.
In order to overcome that situation, the multithreaded pipeline architecture and the wive pipeline principle are investigated.
A processor of multithreaded architecture puts instructions into a pipeline from distinct instruction streams independent each other. So, the architecture enables the ex
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treme deep pipelining if the application program is decomposed to a lot of independent threads.
When a processor operates in the wave pipeline principle, it can break the limit of switching and propagation delays, because the clock period is determined with the difference between maximum and minimum path delay of pipeline stages.
The authors are investigating design methodologies of the wave pipelining multithreaded processors, especially, the delay balancing method considering wiring length and low power consumption design if introducing wave pipelining.
The report consists of the following eight parts.
1. Performance of a multithreaded pipeline processor.
2. A pipelined cache memory for multithreaded pipeline processors.
3. Improvement of a delay balancing method for wave pipelining.
4. Evaluation of a variable thread number processor.
5. Optimization of wiring structures.
6. A high throughput memory system design for a multithreaded processor.
7. More improvement for delay balancing method.
8. A low power consumption design for wave pipelining processors. Less
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