| Project/Area Number |
10480060
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| Research Category |
Grant-in-Aid for Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | KYOTOUNIVERSITY |
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Principal Investigator |
KAMBAYASHI Yahiko Kyoto University, Graduate School of Informatics, Professor, 情報学研究科, 教授 (00026311)
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| Co-Investigator(Kenkyū-buntansha) |
SAWADA Sunao Kyushu University, Graduate School of Information Science and Electrical Engineering Assistant Professor, 大学院・システム情報科学研究科, 助手 (70235464)
TAKAKURA Hiroki Kyoto University, Data Processing Center, Associate Professor, 大型計算機センター, 助教授 (70281144)
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| Project Period (FY) |
1998 – 2000
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| Project Status |
Completed (Fiscal Year 2000)
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| Budget Amount *help |
¥11,600,000 (Direct Cost: ¥11,600,000)
Fiscal Year 2000: ¥2,500,000 (Direct Cost: ¥2,500,000)
Fiscal Year 1999: ¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 1998: ¥5,500,000 (Direct Cost: ¥5,500,000)
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| Keywords | Logic Optimization / Logic Synthesis / Transduction Method / Error Compensation Method / Pass Transistor / CMOS / Annealing Method / Permissible Function / 最適論理化 / FPGA / 拡張許容関数集合 / 論理設計 |
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| Research Abstract |
Reuse of design data and design automation of logic circuits becomes important because logic circuits become to have large and complex structure. Though the CAD database is an indispensable technology to realize reuse of design data, it is difficult to integrate existing design methods and database technology as it is. Thus we have studied and improved design methods of logic circuits suitable for databases, which realize the CAD database. The themes of this research includes an improvement of the transduction method, development of a method for FPGA logic circuit design, development of a reuse technique of logic circuits, and development of a technique for saving power consumption of logic circuits.
In 1998, we have developed SSPFs (Super Set of Permissible Functions) that extend CSPFs (Compatible Sets of Permissible Functions) used by the transduction method and increased the degree of freedom in transformation of logic circuits. We also have proposed PSPFDs (Priority based SPFDs) tha
… More
t generalize the notion of SPFDs representing the logical degree of freedom of FPGA circuits and achieved a 40% reduction in the area of circuits. We have proposed a new algorithm for logic circuit design with saving power consumption that uses 3-state CMOS and realized the function assignment considering saving power consumption.
In 1999, we have developed two methods : a method that applies simulated annealing, one of metaheuristics, to the transduction method, and a method of logic optimization based on the notion of PF (Permissible Function) used by the transduction method for a pass transistor logic that is expected to realize more low power consumption circuits than existing CMOS logic.
In 2000, first, we have improved the optimization method for pass transistor logic circuits. we have found errors in a book of logic circuits, published more than 35 years ago, that collects minimal circuits calculated by hand by the improved method. Secondly, the development of a optimization method of CMOS logic have progressed. We have applied the method to the pass transistor logic that developed the preceding year for decreasing the number of transistors in logic gates. We also have introduced and applied the transduction method to reduce the number of logic gates. More effective optimization method of logic circuits have been developed by integrating the CMOS logic optimization method and the transduction method. Less
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