| Project/Area Number |
10480062
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| Research Category |
Grant-in-Aid for Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Kyoto Institute of Technology |
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Principal Investigator |
SHIBAYAMA Kiyoshi Kyoto Inst.Tech., Eng.& Design, Prof., 工芸学部, 教授 (70127091)
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| Co-Investigator(Kenkyū-buntansha) |
NIIMI Haruo Kyoto Sangyo Univ., Eng., Prof., 工学部, 教授 (40144331)
HIRATA Hiroaki Kyoto Inst.Tech., Eng.& Design, Associate Prof., 工芸学部, 助教授 (90273549)
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| Project Period (FY) |
1998 – 2000
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| Project Status |
Completed (Fiscal Year 2000)
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| Budget Amount *help |
¥9,200,000 (Direct Cost: ¥9,200,000)
Fiscal Year 2000: ¥3,100,000 (Direct Cost: ¥3,100,000)
Fiscal Year 1999: ¥2,800,000 (Direct Cost: ¥2,800,000)
Fiscal Year 1998: ¥3,300,000 (Direct Cost: ¥3,300,000)
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| Keywords | Computer Architecture / Processor Hierarchy / Memory hierarchy / Processor Architecture / Memory Architecture / Processor-Memory Bus Architecture / プロセッサ / プロセッサ-メモリ間通信 / プロセッサーメモリ間転送 / メッセージ通信 / 性能評価 |
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| Research Abstract |
Today's computer system consists mainly of a processor, a memory module, and an I/O (communication) subsystem as hardware resources, connected with each other.
A processor, which is a kernel processing the information has the two ways for acquiring data to operate. One is a memory access for loadins/storing data from/to memory of an internal resource on a computer system, and the other is a communication for sending/receiving data from/to the other external hardware. The inter-processor communication is an essential faculty to develop a parallel computer system, which is constructed with a number of processors connected with an interconnection network.
A latency of the memory access and an inter-processor communication becomes a major factor of disturbing the improvement of total performance of computer systems. As the operating frequuency of microprocessors have highly increased, the relative cost of memory accesses has increased. On the other hand, although the recent high-speed network hardware enhances the data transfer rate in electric level, a large communication overhead in both of software and hardware, except the data transfer itself, is still disturbing the performance improvement of communications. Considering these states, we need to reconstruct the processor-memory architecture by investigating the optimal trade-off point among processor, memory, and communication. This research presents hierarchical processor architecture for high-speed memory access and inter-processor communication with two novel schemes.
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