| Project/Area Number |
10555098
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 展開研究 |
|---|
| Research Field |
Electronic materials/Electric materials
|
|---|
| Research Institution | Hokkaido University |
|---|
Principal Investigator |
HASEGAWA Hideki Hokkaido Univ., Grad. School of Eng., Pro., 大学院・工学研究科, 教授 (60001781)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
KASAI Seiya Hokkaido Univ., Grad. School of Eng., Inst., 大学院・工学研究科, 助手 (30312383)
FUJIKURA Hajime Hokkaido Univ., Grad. School of Eng., Ass. Pro., 大学院・工学研究科, 助教授 (70271640)
HASEZUME Tamotsu Hokkaido Univ., RCIQE, Ass. Pro., 量子界面エレクトロニクス研究センター, 助教授 (80149898)
UEDA Daisuke Matsushita Electronics Corp., Semi. Dev. Res. Cen., Councilor, 半導体デバイス研究センター, 先端技術開発担当参事(研究職)
|
|---|
| Project Period (FY) |
1998 – 1999
|
| Project Status |
Completed (Fiscal Year 1999)
|
| Budget Amount *help |
¥12,900,000 (Direct Cost: ¥12,900,000)
Fiscal Year 1999: ¥4,300,000 (Direct Cost: ¥4,300,000)
Fiscal Year 1998: ¥8,600,000 (Direct Cost: ¥8,600,000)
|
|---|
| Keywords | ultrathin Si quantum well / InP-based materials / insulated-gate structure / ECR plasma process / Fermi level pinning / unified DIGS model / InP MISFET / ultra high-frequency and high speed devices / 電気化学プロセス / ショットキー極限 / 金属 / 半導体界面 / インジウムリン / パルス法 |
|---|
| Research Abstract |
The purpose of this study is to provide a breakthrough for realization of InP-based ultra high-frequency and high-speed devices using a novel insulated gate structure having a "ultrathin Si quantum well". The main results obtained are listed below:
l ) Novel in-situ characterization methods for semiconductor free surfaces as well as MIS interfaces during the interface formation process were established based on a UHV-based contactless C-V method and a photoluminescence surface state spectroscopy (PLSィイD13ィエD1).
2) By combining these methods with a UHV-STM/STS and a XPS analyses, the pinning center was found not to be a point with discrete deep level, but to be an area with gap state continuum. This seems to support the unified disorder induced gap state (DIGS) model for Fermi level pinning proposed by our group, which is the basis of the concept of present "insulated-gate structure having ultrathin Si quantum well".
3) The insulated-gate structure having ultrathin Si quantum well with precisely controlled quantum well thickness was successfully realized by MBE growth of ultrathin psedomorphic Si layer on the InP-based materials and subsequent thinning of the Si layer by ECR plasma-induced partial nitridation.
4) Under the optimum ECR nitridation condition, this process realized the InP MIS structure with extremely low interface state density of 2x10ィイD110ィエD1cmィイD1-2ィエD1eVィイD1-1ィエD1. This value is the best of all the oxide-free InP MIS structures reported so far.
5) An InP MISFETs fabricated using the present insulated gate structure having the ultrathin Si quantum well exhibited excellent gate control capability, high effective electron mobility and stable operation. The drift of the drain current was found to be as small as 1.9% after 10ィイD14ィエD1 s operation.
|
