| Project/Area Number |
10555118
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| Research Category |
Grant-in-Aid for Scientific Research (B).
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | University of Tokyo |
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Principal Investigator |
SAKURAI Takayasu Center of Collaborative Research, University of Tokyo, 国際・産学共同研究センター, 教授 (90282590)
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| Co-Investigator(Kenkyū-buntansha) |
HIRAMOTO Toshirou VLSI Design and Education Center, University of Tokyo, 大規模集積システム設計教育研究センター, 助教授 (20192718)
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| Project Period (FY) |
1998 – 2000
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| Project Status |
Completed (Fiscal Year 2000)
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| Budget Amount *help |
¥12,600,000 (Direct Cost: ¥12,600,000)
Fiscal Year 2000: ¥3,100,000 (Direct Cost: ¥3,100,000)
Fiscal Year 1999: ¥5,600,000 (Direct Cost: ¥5,600,000)
Fiscal Year 1998: ¥3,900,000 (Direct Cost: ¥3,900,000)
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| Keywords | LSI / Scaling / Wiring Delay / Repeater / Simulated Diffusion / Super Connect / simulated diffusion |
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| Research Abstract |
Recently interconnect was minute as scaling of transistor in LSI, interconnects parasitic resistance and capacitance will be one of the biggest source of wiring delay. Scaling law decreases gate delay, but to decrease total delay of circuit is difficult because of increment of interconnect delay.
Repeater insertion is one of the important technique of decrease interconnect delay. The method divide long interconnect by inserting repeaters. In this study, we construct new model for delay time calculation. This study suggested new method for repeater insertion that optimum delay time of interconnects with branch. Power consumption, Power-Delay product and repeater size and number for optimum design was showed, and the relation between power consumption and delay time was considered. Repeater intervals are settled uniquely according to technology node and interconnect length. Because shape and spacing of interconnects are provided by technology node.
Recently, effects of inductance attract considerable attention. But practical side of effects of inductance are not investigated yet when interconnects are divided by repeaters. In this study, we try to measure waveform inside LSI that include waveform detector using sensitive comparator. The waveform will be a source of inductance extraction.
We proposed concept of Super Connect to unite that mentioned above. Super connect means interconnect that have about 10 μm length. Conservative scaling concept cannot keep increment of power consumption and wiring delay. This concept suggest enlarge interconnects as technology nodes advances. Consequently, interconnects resistance, power consumption, interconnect layer and wiring delay will decrease.
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