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The Architecture of a Next Gereration Hultimedia Server

Research Project

Project/Area Number 10558045
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 計算機科学
Research InstitutionKYOTO UNIVERSITY

Principal Investigator

TOMITA Shinji  Kyoto Univ., Grad School of Informatics, Prof., 情報学研究科, 教授 (40026323)

Co-Investigator(Kenkyū-buntansha) NISHIZAWA Teiji  Matsushita Elictvic Corp. Multimedia Development Center, Teamleader, マルチメディア開発センタ, チームリーダ(研究職)
GOSHIMA Masahiro  Kyoto Univ., Grad School of Informatics, Research Associate, 情報学研究科, 助手 (90283639)
MORI Shin-ichiro  Kyoto Univ., Grad School of Informatics, Associate Prof., 情報学研究科, 助教授 (20243058)
Project Period (FY) 1998 – 1999
Project Status Completed (Fiscal Year 1999)
Budget Amount *help
¥12,700,000 (Direct Cost: ¥12,700,000)
Fiscal Year 1999: ¥9,700,000 (Direct Cost: ¥9,700,000)
Fiscal Year 1998: ¥3,000,000 (Direct Cost: ¥3,000,000)
KeywordsHultimedia / Sewer / Volume Rendering / Speculation / DataHow / Java / 専用計算機 / 返用画像 / 専用並列計算機 / 3次元グラフィックス / プロセッサアーキテクチャ / データ駆動型計算機 / 制御駆動型計算機
Research Abstract

The project consists of following three themes :
1. ReVolver/C40: a volume rendering architecture
We developed a prototype of the ReVolver/C40 volume rendering architecture as a visualization mechanism for the next generation multimedia server. Volume rendering, which is a scheme to directly visualize volume data, is hard to execute in real-time because of bank conflict on the memory. ReVolver/C40 has a memory system free from bank conflict. The evaluation result of developed prototype shows that ReVolver/C40 can render about six frames per second.
2. A hybrid processor architecture between control-and data-driven
We proposed Dualflow as a processor architecture for the next generation multimedia server. The architecture does not define registers and the instructions pass operands directly. Superscalars implements the instruction scheduling logic with a CAM, and the logic may become the critical path of the system. Dualflow can replace the CAM with a RAM. We developed a compiler and evaluated it with the SPEC benchmark. The result shows it inserts a lot of extra instructions, and needs another optimization to remove them.
3. High-speed Java bytecode execution
High-speed execution of Java bytecode is necessary for the next generation multimedia server. We proposed a Value Look-aside Buffer. Value Look-aside Buffer memorizes pairs of pre-and post-states of the past executions. When the machine states matches one of the memorized pre-states, it can eliminate the execution just by replacing it with the post-state. The results of the simulation study shows it can speeds-up about 47.1% at best.

Report

(3 results)
  • 1999 Annual Research Report   Final Research Report Summary
  • 1998 Annual Research Report
  • Research Products

    (9 results)

All Other

All Publications (9 results)

  • [Publications] 五島正裕: "Dualflowアーキテクチャの提案"並列処理シンポジウムJSPP2000. (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Masnhiro Goshima: "Proposal of the Dualflow architectare"Joint Symposium on Parallel Processil JSPP2000. (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 五島 正裕: "Dualflowアーキテクチャの提案"並列処理シンポジウム JSPP2000. (2000)

    • Related Report
      1999 Annual Research Report
  • [Publications] Shin-ya Goto: "Optimized Code Generation for Heterogeneus Computing Environment Using Parallelizing Compilor TINPAR" Proc.Int.Cont.on Parallel Architectures and Compiler Techniques. 426-433 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 山本 孝伸: "超並列計算機JUMP-1のクラスタの実装及び予備的性能評価" 情報研報 98-ARC-130. 7-12 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 秤谷 雅史: "超並列計算機JUMP-1における分散共有メモリ管理の実装とその評価" 情報研報 98-ARC-130. 1-6 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 五島 正裕: "Dual-How:制御駆動とデータ駆動を融合したプロセッサーアーキテクチャ" 情報研報 98-ARC-130. 115-120 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 古谷 直樹: "ボリュームレンダリング専用並列計算機 ReVolver/c40の性能評価" 情報研報. (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] 森 眞一郎: "並列計算機アーキテクトからみた計算機クラスタ" 情報処理. Vol.39,No.11. 46-50 (1998)

    • Related Report
      1998 Annual Research Report

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Published: 1998-04-01   Modified: 2016-04-21  

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