Project/Area Number |
10558045
|
Research Category |
Grant-in-Aid for Scientific Research (B)
|
Allocation Type | Single-year Grants |
Section | 展開研究 |
Research Field |
計算機科学
|
Research Institution | KYOTO UNIVERSITY |
Principal Investigator |
TOMITA Shinji Kyoto Univ., Grad School of Informatics, Prof., 情報学研究科, 教授 (40026323)
|
Co-Investigator(Kenkyū-buntansha) |
NISHIZAWA Teiji Matsushita Elictvic Corp. Multimedia Development Center, Teamleader, マルチメディア開発センタ, チームリーダ(研究職)
GOSHIMA Masahiro Kyoto Univ., Grad School of Informatics, Research Associate, 情報学研究科, 助手 (90283639)
MORI Shin-ichiro Kyoto Univ., Grad School of Informatics, Associate Prof., 情報学研究科, 助教授 (20243058)
|
Project Period (FY) |
1998 – 1999
|
Project Status |
Completed (Fiscal Year 1999)
|
Budget Amount *help |
¥12,700,000 (Direct Cost: ¥12,700,000)
Fiscal Year 1999: ¥9,700,000 (Direct Cost: ¥9,700,000)
Fiscal Year 1998: ¥3,000,000 (Direct Cost: ¥3,000,000)
|
Keywords | Hultimedia / Sewer / Volume Rendering / Speculation / DataHow / Java / 専用計算機 / 返用画像 / 専用並列計算機 / 3次元グラフィックス / プロセッサアーキテクチャ / データ駆動型計算機 / 制御駆動型計算機 |
Research Abstract |
The project consists of following three themes : 1. ReVolver/C40: a volume rendering architecture We developed a prototype of the ReVolver/C40 volume rendering architecture as a visualization mechanism for the next generation multimedia server. Volume rendering, which is a scheme to directly visualize volume data, is hard to execute in real-time because of bank conflict on the memory. ReVolver/C40 has a memory system free from bank conflict. The evaluation result of developed prototype shows that ReVolver/C40 can render about six frames per second. 2. A hybrid processor architecture between control-and data-driven We proposed Dualflow as a processor architecture for the next generation multimedia server. The architecture does not define registers and the instructions pass operands directly. Superscalars implements the instruction scheduling logic with a CAM, and the logic may become the critical path of the system. Dualflow can replace the CAM with a RAM. We developed a compiler and evaluated it with the SPEC benchmark. The result shows it inserts a lot of extra instructions, and needs another optimization to remove them. 3. High-speed Java bytecode execution High-speed execution of Java bytecode is necessary for the next generation multimedia server. We proposed a Value Look-aside Buffer. Value Look-aside Buffer memorizes pairs of pre-and post-states of the past executions. When the machine states matches one of the memorized pre-states, it can eliminate the execution just by replacing it with the post-state. The results of the simulation study shows it can speeds-up about 47.1% at best.
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