Evaluation of Si/Ge ALE super lattice with high depth resolution AES method
| Project/Area Number |
10650321
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Teikyo University of Science and Technology |
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Principal Investigator |
UCHIDA Yasutaka Teikyo Univ.of Sci. and Tech., Undergraduate School of Science and Engineering, Associate professor, 理工学部, 助教授 (80134823)
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| Co-Investigator(Kenkyū-buntansha) |
SUGAHARA Satoshi Tokyo Institute of Technology, Faculty of Engineering, Research associate, 工学部, 助手 (40282842)
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| Project Period (FY) |
1998 – 1999
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| Project Status |
Completed (Fiscal Year 1999)
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| Budget Amount *help |
¥3,300,000 (Direct Cost: ¥3,300,000)
Fiscal Year 1999: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 1998: ¥2,600,000 (Direct Cost: ¥2,600,000)
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| Keywords | AES / Si / Ge hetero interface / super lattice / AFM / CAICISS / ALE / XPS / サーファクタント / 組成分布 / 平坦性 |
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| Research Abstract |
In order to evaluate abruptness of Si/Ge hetero interface, we have developed novel analysis method for depth profile for Auger Electron Spectroscopy (AES). By optimizing accelerating voltage of Ar sputtering, electron-beam current density and electron-beam diameter, we have confirmed that transition region of Si and SiO2 interface which was well known as a atomically flat by using Si(111) just wafer and oxidizing very carefully was lower than 1nm. Further more, escape depth λ of Auger electron has strong influence on the evaluation of atomically abrupt interface although it is a short as 0.5nm in a low kinetic energy region less that 100eV. Then deduced transition region obtained from calculated depth profiles was as narrow as 0.35nm. This value was almost same as 1 atomic layer. Also we have confirmed that flatness of etched surface was kept in a very good condition by AFM measurement.
We have applied this novel method to Si/Ge hereto-super lattice which consists of 3 Mono Layer (ML) of Ge and 7ML of Si by using atomic layer epitaxy (ALE). It was confirmed that observed AES intensity distribution along the depth was represented to the supper lattice structure. Signal intensity of Ge was sharply changed at Si/Ge interfaces and this means that segregation of Ge was well suppressed. According to this experiment, flatness of both Si and Ge buffer layers had important role for suppressing the strain of the supper lattice. Thus we have optimizing the growth condition of buffer layer to suppressing growth rate lower than 0.5nm/min. Runs of Ge and Si buffer layer were 0.15nm and 0.1nm, respectively. Early stage of ALE was investigated by using CAICISS. Layer by layer growth was confirmed for the ALE method.
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Report
(3 results)
Research Products
(13 results)
