| Project/Area Number |
10650331
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
電子デバイス・機器工学
|
|---|
| Research Institution | Chiba University |
|---|
Principal Investigator |
ITO Hideo Chiba University, Faculty of Engineering, Professor, 工学部, 教授 (90042647)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
KITAKAMI Masato Chiba University, Faculty of Engineering, Lecturer, 工学部, 講師 (20282832)
OHMAMEUDA Toshiaki Chiba University, Faculty of Engineering, Assistance, 助教授 (60272340)
KANEKO Keiichi Chiba University, Faculty of Engineering, Lecturer, 助教授 (20194904)
|
|---|
| Project Period (FY) |
1998 – 2000
|
| Project Status |
Completed (Fiscal Year 2000)
|
| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,900,000)
Fiscal Year 2000: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 1999: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 1998: ¥2,400,000 (Direct Cost: ¥2,400,000)
|
|---|
| Keywords | Fault Tolerance / VLSI Chip / Architecture / FPGA / Defect / Fault / Reconfiguration / Error Recovery / 2次キャッシュ / 欠陥回避 / 故障検査 / 2重バス / 多重系動作 / 階層構成 / コンカレント誤り検出 |
|---|
| Research Abstract |
The target of this research was to develop the techniques making chip yield increase for fabrication and making chip fault tolerance during notmal operation for general purpose VLSI chip which would be used after ten years. The technieques were developed in the architecture design, logical design, and circuit design. We have got the following results.
(1) Reconfiguration method for defects and faults
We have got the following 3 resuts for defect and fault tolerance in reconfiguring FPGA chips. (1.1) Reconfiguration designs against defects and faults in CLB (Configuration Logic Block), (1.2) Reconfiguration designs against defects and faults in wiring area, and (1.3) Diagnosis and Reconfiguration designs against defects and faults in SRAM.
(2) Easily testable logic design
We have got the following 3 resuts. (2.1) Short test sequence generation for sequential circuits by connecting test vectors using a state transition diagram, (2.2) FF selection method for partial scan FFs, A study for the relation between reset FFs and fault coverage, and BIST (Built-In Self-Test) using check points, and (2.3) FPGA design and test generation for the high speed testing.
(3) Architecure design for easy error recovery
We have got the following 4 resuts. (3.1) LPU-MPU architecture design for LPU-MPU-HPU, 3-lebel hierarchical, parallel processing system, (3.2) Checkpointing method for error recovery in parallel processing systems, (3.3) Multiple mode system design with high reliable mode and normal modes, and (3.4) Routing algorithms for parallel systems with faults in nodes or links.
|
