| Project/Area Number |
10650335
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Fukuoka University |
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Principal Investigator |
MOSHNYAGA Vashily Fukuoka Univ., Fac. Engin., Assoc. Prof, 工学部, 助教授 (40243050)
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| Co-Investigator(Kenkyū-buntansha) |
TAMARU Keikichi Okayama Univ. Sci., Fac. Engin., Prof., 工学部, 教授 (10127102)
TSURUTA Naoyuki Fukuoka Univ., Fac. Engin., Lecturer, 工学部, 講師 (60227478)
SHUDO Kosho Fukuoka Univ., Fac. Engineering., Professor, 工学部, 教授 (70078632)
KOBAYASHI Kazutoshi Kyoto Univ., Graduate Sch. Engin. Res. Assoc., 工学研究科, 助手 (70252476)
ONODERA Hidetoshi Kyoto Univ., Graduate Sch. Engin. Prof, 工学研究科, 教授 (80160927)
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| Project Period (FY) |
1998 – 1999
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| Project Status |
Completed (Fiscal Year 1999)
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| Budget Amount *help |
¥3,800,000 (Direct Cost: ¥3,800,000)
Fiscal Year 1999: ¥1,600,000 (Direct Cost: ¥1,600,000)
Fiscal Year 1998: ¥2,200,000 (Direct Cost: ¥2,200,000)
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| Keywords | Motion Estimation / Architecture / Design Techniques / Memory Distribution / Low Power / LSI / Video Compression / プロセッサ アレー |
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| Research Abstract |
(a) Development of a Memory Based on Architecture and its chip implementation for Video Motion Estimation.
We proposed a new concept of Memory-Based Architecture and presented its implementation for the task of video motion-estimation. Due to video memory distribution and sharing, the architecture ensure feasible solution for the HDTV picture format with the half memory requirement. To evaluate the architecture, a prototype LSI chip have been designed and fabricated.
(b) Development of New Algorithmic and Architectural Techniques for Reducing Energy Consumption of Motion Estimation Hardware.
A new computationally adaptive algorithm for the block matching video motion estimation have been proposed. Unlike existing methods, the algorithm adjusts the computation to the picture contents, reducing the number of operations by a factor of four while maintaining the highest quality of results. A new processor architecture to support the proposed algorithm have been developed.
(c) Development of New Circuit Techniques for Reducing Energy Dissipation.
Several new schemes to adaptively adjust the bit-with to input data variation have been proposed. Unlike conventional techniques, the schemes can dynamically disable the hardware bits whose values remain unchanged, this reducing unnecessary signal variations as much as half without affecting the processing accuracy. The schemes are simple and easy in implementation.
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